PEB2045 datasheet(3/53 Pages) SIEMENS

Part #	PEB2045

Description	Memory Time Switch CMOS (MTSC)

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Manufacturer	SIEMENS [Siemens Semiconductor Group]

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PEB 2045

PEF 2045

Semiconductor Group

3

1.1

Pin Definitions and Functions

Pin No.

P-LCC

Pin No.

P-DIP

Symbol

Input (I)

Output (O)

Function

11

V

SS

I

Ground (OV)

3

2

SP

I

Synchronization Pulse: The PEx 2045 is

synchronized relative to the PCM system via

this line.

4

7

9

11

13

14

15

16

17

18

19

3

5

7

9

11

12

13

14

15

16

17

IN1

IN5

IN9

IN13

IN14

IN15

IN10

IN11

IN6

IN7

IN2

I

PCM-Input Ports: Serial data is received at

these lines at standard TTL levels.

5

8

10

12

4

6

8

10

IN0/TSC0

IN4/TSC1

IN8/TSC2

IN12/TSC3

I/O

PCM-Input Port / Tristate Control: In standard

configuration these pins are used as input lines,

in primary access configuration they supply

control signals for external devices.

20

18

IN3/DCL

I/O

PCM-Input Port / Data Clock: In standard

configuration IN3 is the PCM input line 3, in

primary access configuration it provides a

2048-kHz data clock for the synchronous

interface.

21

19

A0

I

Address 0: When high, the indirect register

access mechanism is enabled. If A0 is logical 0

the mode and status registers can be written to

and read respectively.

22

20

CS

I

Chip Select: A low level selects the PEx 2045

for a register access operation.

23

21

V

DD

I

Supply voltage: 5 V

± 5 %.

24

22

RD

I

Read: This signal indicates a read operation

and is internally sampled only if CS is active.

The MTSC puts data from the selected internal

register on the data bus with the falling edge of

RD. RD is active low.

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PEB2045 Datasheet(PDF) 3 Page - Siemens Semiconductor Group

PEB2045 Datasheet(HTML) 3 Page - Siemens Semiconductor Group

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