MPC106 PCI Bridge/Memory Controller Hardware Specifications

9

Electrical and Thermal Characteristics

Figure 3 provides the input timing diagram for the 106.

Table 7. Input AC Timing Specifications

Num

Characteristic

66 MHz

83.3 MHz

Unit

Notes

Min

Max

Min

Max

10a Group I input signals valid to 60x Bus Clock (input setup)

4.0

3.5

ns

1,2,3

10a Group II input signals valid to 60x Bus Clock (input setup)

3.5

3.5

ns

1,2,4

10a Group III input signals valid to 60x Bus Clock (input setup)

3.0

2.5

ns

1,2,5

10a Group IV input signals valid to 60x Bus Clock (input setup)

5.0

4.0

ns

1,2,6

10b Group V input signals valid to SYSCLK (input setup)

7.0

7.0

ns

7,8

10b Group VI input signals valid to SYSCLK (input setup)

7.0

7.0

ns

7,9

11a 60x Bus Clock to group I–IV inputs invalid (input hold)

0

—

0

—

ns

3,4,5,6

11b SYSCLK to group V–VI inputs invalid (input hold)

–0.5

—

–0.5

—

ns

8,9

HRST pulse width

255 x

100 µs

—

255 x

100 µs

——

10c Mode select inputs valid to HRST (input setup)

—

—

ns

10,

11,12

11c HRST to mode select input invalid (input hold)

1.0

—

1.0

—

ns

10, 12

Notes:

edge of SYSCLK. Both input and output timings are measured at the pin (see Figure 3).

synchronized to SYSCLK).

BR[0–4], BRL2, XATS, LBCLAIM, ADS, BA0, TV and HIT (when configured for external L2)

CI, GBL, AACK, and TA.

(when configured for internal L2 controller).

IRDY, TRDY, STOP, PAR, PERR, SERR, LOCK, FLSHREQ, and ISA_MASTER.

RCS0, FOE, and DBG0 configuration inputs.

numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in

nanoseconds) of the parameter in question.