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SY89536L Datasheet(PDF) 3 Page - Micrel Semiconductor

Part No. SY89536L
Description  3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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SY89536L Datasheet(HTML) 3 Page - Micrel Semiconductor

 
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SY89536L
Micrel
PIN DESCRIPTION
Power
Pin Number
Pin Name
Pin Function
60, 61
V
CC_Logic
Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
62
V
CCA
Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
55
V
CCOA
Power for Output Drivers: Connect V
CCOA and VCCOC pins to 3.3V supply and VCCOB
30, 31, 50
V
CCOB
pins to 1.8V supply.
21
V
CCOC
4, 9, 25, 63, 29
GND
Ground: All GND pins must be tied together on the PCB. Exposed pad must be
(exposed pad)
soldered to a ground plane.
Configuration
Pin Number
Pin Name
Pin Function
4
VCO_SEL
LVTTL/CMOS Compatible Input: Selects between internal or external VCO. When
tied LOW (GND) internal VCO is selected. For external VCO, leave floating (default
condition is logic HIGH). Internal 25kΩ pull-up.
5, 6
PSEL(1:0)
LVTTL/CMOS Compatible Input: Controls input frequency pre divider. Internal 25kΩ
pull-up. Default is logic HIGH. See
“Pre-Divide Frequency Select” table.
7
LOOP REF
Analog Input/Output: Provides the reference voltage for PLL loop filter.
8
LOOP FILTER
Analog Input/Output: Provides the loop filter for PLL. See
“External Loop Filter
Considerations” for loop filter values.
13,14,15,16
M (3:0)
LVTTL/CMOS Compatible Input: Used to change the PLL feedback divider. Internal 25kΩ
pull-up. M0 = LSB. Default is logic HIGH. See
“Feedback Divide Select” table.
22, 23, 24
FSEL_C (2:0)
LVTTL/CMOS Compatible Input: Bank C post-divide select. Internal 25kΩ pull-up.
Default is logic HIGH. See
“Post-Divide Frequency Select” table. FSEL_C0 = LSB.
26, 27, 28
FSEL_B (2:0)
LVTTL/CMOS Compatible Input: Bank B post-divide select. Internal 25kΩ pull-up.
Default is logic HIGH. See
“Post-Divide Frequency Select” table. FSEL_B0 = LSB.
56, 57, 58
FSEL_A (2:0)
LVTTL/CMOS Compatible Input: Bank A post-divide select. Internal 25kΩ pull-up.
Default is logic HIGH. See
Post-Divide Frequency Select” table. FSEL_A0 = LSB.
59
OUT_SYNC
Banks A, B, C Output Synchronous Control: (LVTTL/CMOS compatible).
Internal 25kΩ pull-up. After any bank has been programmed, toggle with a HIGH-LOW-HIGH
pulse to resynchronize all output banks.
Input/Output
Pin Number
Pin Name
Pin Function
1, 2, 3
NC
No Connect: Leave floating.
10, 11
REFCLK,
Reference Input: This flexible input accepts any input TTL/CMOS, LVPECL, LVDS,
/REFCLK
HSTL, SSTL logic levels. See
“Input Interface” section.
12
VBB_REF
Reference Output Voltage. Used for single-ended input. Maximum sink/source current = 0.5mA.
51, 52, 53, 54
QA1 to QA0
Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A (0:2).
Terminate outputs with 50Ω to VCC –2V. See “Output Termination Recommendations”
section.
32–49
QB8 to QB0
Bank B Output Drivers: Differential HSTL outputs. See
“Output Termination Recommendations”
section. Output frequency is controlled by FSEL_B (0:2).
17, 18, 19, 20
QC1 to QC0
Bank C 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_C (0:2).
Terminate outputs with 50Ω to VCC–2V. See “Output Termination Recommendations” section.
64
NC
No Connect: Leave floating.


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