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MN3674 Datasheet(PDF) 3 Page - Panasonic Semiconductor

Part No. MN3674
Description  Color CCD Linear Image Sensor with 512 Pixels for R and B Colors/1024 Pixels for G Color
Download  9 Pages
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Maker  PANASONIC [Panasonic Semiconductor]
Homepage  http://www.panasonic.com/industrial/
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MN3674 Datasheet(HTML) 3 Page - Panasonic Semiconductor

   
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CCD Linear Image Sensor
MN3674
Parameter
Symbol
Condition
min
typ
max
Unit
Shift register clock frequency
Reset clock frequency (=data rate)
Shift register clock rise time
Shift register clock fall time
Vertical transfer clock rise time
Vertical transfer clock fall time
Vertical transfer clock pulse width
Shift clock 1 rise time
Shift clock 1 fall time
Shift clock 1 set up time
Shift clock 1 pulse width
Shift clock 2 rise time
Shift clock 2 fall time
Shift clock 2 set up time
Shift clock 2 pulse width
Shift clock 2 hold time
Reset clock rise time
Reset clock fall time
Reset clock set up time
Reset clock pulse width
Reset clock hold time
f
C
t
R
Cr
Cf
SG1r
SG1f
SG1s
Vr
Rr
Rf
Rs
Rw
Rh
f
t
t
t
t
t
t
t
t
t
t
0.1
0.1
0
0
0
0
5
0
0
0.5
5
0
0
0.5
5
0
0
0
0.7T
100
10
1.0
1.0
20
20
15
15
10
15
15
1.0
10
15
15
1.0
10
1
10
10
200
125
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0
3.0
50
50
50
50
50
50
50
2.0
50
50
50
2.0
50
2
20
20
SG2r
SG2f
SG2s
SG2w
t
t
t
t
Vf
VW
t
t
µs
µs
µs
µs
µs
µs
SG1w
t
SG2h
t
See drive timing diagram (3) fR=1/2T
See drive timing diagram (3) fC=1/2T
See drive timing diagram (3)
ø
and ø should be the same timing.
See drive timing diagram (1)
SG1
V
See drive timing diagram (1)
See drive timing diagram (1)
See drive timing diagram (3)
Parameter
Symbol
Condition
min
typ
max
Unit
Shift register clock frequency
Reset clock frequency (=data rate)
Shift register clock rise time
Shift register clock fall time
Vertical transfer clock rise time
Vertical transfer clock fall time
Vertical transfer clock set up time
Vertical transfer clock pulse width
Vertical transfer clock hold time
Shift clock 1 rise time
Shift clock 1 fall time
Shift clock 1 pulse width
Shift clock 2 rise time
Shift clock 2 fall time
Shift clock 2 set up time
Shift clock 2 pulse width
Reset clock rise time
Reset clock fall time
Reset clock set up time
Reset clock pulse width
Reset clock hold time
fC
t
R
Cr
Cf
SG1r
SG1f
Vr
Rr
Rf
Rs
Rw
Rh
f
t
t
t
t
t
t
t
t
t
0.1
0.1
0
0
0
0
0.5
5
0
0
0
5
0
0
0.5
5
0
0
0.7T
100
100
1.0
1.0
20
20
15
15
1.0
10
1
15
15
10
15
15
1.0
10
10
10
200
125
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0
3.0
50
50
50
50
2.0
50
2
50
50
50
50
50
2.0
50
20
20
SG2r
SG2f
SG2s
SG2w
t
t
t
t
Vf
Vs
t
t
µs
µs
µs
µs
SG1w
t
See drive timing diagram (3) fR=1/2T
See drive timing diagram (3) fC=1/2T
See drive timing diagram (3)
ø
and ø should be the same timing.
See drive timing diagram (2)
SG1
V
See drive timing diagram (2)
See drive timing diagram (2)
See drive timing diagram (3)
Vw
t
Vh
t
µs
µs
Timing conditions (without 1-line delay operation) (Ta=0 to + 60˚C)
Timing conditions (during 1-line delay operation) (Ta=0 to + 60˚C)


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