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MN3611RE Datasheet(PDF) 5 Page - Panasonic Semiconductor |
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MN3611RE Datasheet(HTML) 5 Page - Panasonic Semiconductor |
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MN3611RE CCD Linear Image Sensor ø ø ø ø ø 90% 10% 90% tSh tSW tSs 1 SG tSr tSf tCr tCf 90% 10% 90% 10% 50% 10% 90% 50% tRS tRh tRW tRf tRr tOS 90% 1 OS DS 2 R T Reference level Signal output voltage Blank feed (for 8 pixels) Black reference pixel signal (for 52 pixels) Invalid pixel signal (for 3 pixels) Valid pixel signal (for 2160 pixels) Invalid pixel signal (for 3 pixels) Note) Repeat the transfer pulses (cp) for more than 1114 periods. ø DS OS SG ø 1 ø 2 ø R Integration Time (Tint.) 1 2 3 4 6 7 8 9 10 11 58 59 60 61 62 63 64 65 66 2222 2224 2226 2223 2225 1 2 3 4 6 7 8 B 1 B2 B 50 B51 B52 D 1 D2 D3 R G B 2159 2160D 4 D5 D6 1 1 1 s Construction of the Image Sensor The MN3611RE can be made up of the three sections of—a) photo detector region, b) CCD transfer region (shift register), and c) output region. a) Photo detector region • The photoelectric conversion device consists of an 11µm floating photodiode and a 3µm channel stopper for each pixel, and 2160 of these devices are linearly arranged side by side at a pitch of 14µm. • The photo detector's windows are 14µm × 14µm squares and light incident on areas other than these windows is optically shut out. • The photo detector is provided with 52 optically shielded pixels (black dummy pixels) which serve as the black reference. b) CCD Transfer region (shift register) • The light output that has been photoelectrically converted is s Timing Diagram (1) I/O timing (2) Drive timing transferred to the CCD transfer for each odd and even pixel at the timing of the shift clock (øSG). The optical signal electric charge transferred to this analog shift register is successively transferred out and guided to the output region. • A buried type CCD that can be driven by a two phase clock (ø1, ø2) is used for the analog shift register. c) Output region • The signal charge that is transferred to the output region is sent to the detector where impedance transformation is done using two source follower stages. • The DC level component and the clock noise component not containing optical signals are output from the DS pin. • By carrying out differential amplification of the two outputs OS and DS externally, it is possible to obtain an output signal with a high S/N ratio by reducing the clock noise, etc. |
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