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MC74HC299 Datasheet(PDF) 3 Page - Motorola, Inc

Part No. MC74HC299
Description  8-Bit Bidirectional Universal Shift Register with Parallel I/O
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC74HC299 Datasheet(HTML) 3 Page - Motorola, Inc

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MC74HC299
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
– 55 to
25
_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
5.0
25
29
4.0
20
24
3.4
17
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to QA′ or QH′
(Figures 1 and 5)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock to QA thru QH
(Figures 1 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
tPHL
Maximum Propagation Delay, Reset to QA or QH
(Figures 2 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
Maximum Propagation Delay, Reset to QA′ thru QH′
(Figures 2 and 5)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
tPLZ,
tPHZ
Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, QA thru QH
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tTLH,
tTHL
Maximum Output Transition Time, QA′ or QH′
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum Three–State Output Capacitance
(Output in High–Impedance State), QA thru QH
15
15
15
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Package)*, Outputs Enabled
Typical @ 25
°C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Package)*, Outputs Enabled
240
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).


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