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FS6131-01 Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers

Part No. FS6131-01
Description  Programmable Line Lock Clock Generator IC
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Maker  ETC1 [List of Unclassifed Manufacturers]
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FS6131-01 Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers

 
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I
2C is a licensed trademark of Philips Electronics, N.V. Windows and Windows NT are registered trademarks of Microsoft Corporation. American Microsystems, Inc. reserves the right to change detail
specifications as may be required to permit improvements in the design of its products.
FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
1.0
Features
Complete programmable control via I
2Cä-bus
Selectable CMOS or PECL compatible outputs
External feedback loop capability allows genlocking
Tunable VCXO loop for jitter attenuation
Commercial (FS6131-01) and industrial (FS6131-01i)
temperature versions available
2.0
Description
The FS6131-01 is a monolithic CMOS clock genera-
tor/regenerator IC designed to minimize cost and compo-
nent count in a variety of electronic systems. Via the I
2C-
bus interface, the FS6131-01 can be adapted to many
clock generation requirements.
The ability to tune the on-board voltage-controlled crystal
oscillator (VCXO), the length of the Reference and Feed-
back Dividers, their granularity, and the flexibility of the
Post Divider make the FS6131-01 the most flexible
stand-alone phase-locked loop (PLL) clock generator
available.
3.0
Applications
Frequency Synthesis
Line-Locked and Genlock Applications
Clock Multiplication
Telecom Jitter Attenuation
Figure 1: Pin Configuration
1
16
2
3
4
5
6
7
8
15
14
13
12
11
10
9
SCL
SDA
ADDR
VSS
XIN
XOUT
XTUNE
VDD
LOCK/IPRG
EXTLF
VSS
REF
FBK
VDD
CLKP
CLKN
16-pin 0.150" SOIC
Figure 2: Block Diagram
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider (N
F)
Internal
Loop
Filter
EXTLF
I2C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0]
POST2[1:0]
POST1[1:0]
REFDIV[11:0]
FBKDIV[13:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF)
(f
VCO)
LOCK/
IPRG
Post
Divider
(N
Px)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OUTMUX[1:0]
Clock
Gobbler
GBL
(optional)
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK)
CLKP
R
LF
C
LF
C
LP
11
00
10
01
01
00
10
11
1
0
1
0
0
1
1
0
1
0


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