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FS6131-01 Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

 Part No. FS6131-01 Description Programmable Line Lock Clock Generator IC Download 39 Pages Scroll/Zoom 100% Maker ETC1 [List of Unclassifed Manufacturers] Homepage Logo

FS6131-01 Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

 5 / 39 page 5 FS6131-01 FS6131-01 FS6131-01 FS6131-01 Programmable Line Lock Clock Generator IC Programmable Line Lock Clock Generator IC Programmable Line Lock Clock Generator IC Programmable Line Lock Clock Generator IC To enter this mode, set STAT[1] to one and clear STAT[0] to zero. If the CMOS bit is set to one, the LOCK/IPRG pin can display the flag. The flag is always available under software control by reading back the STAT[1] bit, which will be overwritten by the flag in this mode. 4.2.4 Feedback Divider Monitoring The Feedback Divider clock can be brought out the LOCK/IPRG pin independent of the output clock to allow monitoring of the Feedback Divider clock. To enter this mode, set both the STAT[1] and STAT[0] bits to one. The CMOS bit must also be set to one to enable the LOCK/IPRG pin as an output. 4.3 Loop Gain Analysis For applications where an external loop filter is required, the following analysis example can be used to determine loop gain and stability. The loop gain of a PLL is the product of all of the gains within the loop. Establish the basic operating parameters: Set the charge pump current: A I chgpump µ 10 = Set the loop filter values: pF C F C k R LF 220 015 . 0 15 2 1 = = Ω = µ Set the VCO gain (VCOSPD): V MHz A VCO / 230 = Set the Feedback Divider: 3500 = F N Set the Reference frequency (at the input to the Phase Detector: kHz f REF 20 = The transfer function of the Phase Detector and Charge Pump combination is (in A/rad): π 2 chgpump PD I K = The transfer function of the loop filter is (in V/A): ÷ ÷ ÷ ÷ ø ö ç ç ç ç è æ ÷ø ö çè æ + + = 1 2 1 1 1 ) ( sC R sC s K LF LF The VCO transfer function (in rad/s, and accounting for the phase integration that occurs in the VCO) is: s A s K VCO VCO 1 2 ) ( π = The transfer function of the Feedback Divider is: F F N K 1 = Finally, the sampling effect that occurs in the Phase De- tector is accounted for by: REF f s SAMP f s e s K REF ÷ ÷ ÷ ø ö ç ç ç è æ − = ÷ø ö çè æ − 1 ) ( The loop gain of the PLL is: ) ( ) ( ) ( ) ( s K K s K s K K s K SAMP F VCO LF PD LOOP = Figure 8: Loop Gain vs. Frequency 0.01 Frequency (f i) 0.1 0.1kHz 1kHz 10kHz 100kHz 1 10 100

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