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FS6131-01 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. FS6131-01
Description  Programmable Line Lock Clock Generator IC
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Maker  ETC1 [List of Unclassifed Manufacturers]
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FS6131-01 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

 
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FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
The Post Divider performs several useful functions. First,
it allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it
changes the basic PLL equation to
÷÷ø
ö
ççè
æ
÷÷ø
ö
ççè
æ
=
Px
R
F
REF
CLK
N
N
N
f
f
1
.
The extra integer in the denominator permits more flexi-
bility in the programming of the loop for many applica-
tions where frequencies must be achieved exactly.
Note that a nominal 50/50 duty factor is preserved for
selections which have an odd modulus.
4.2
Phase Adjust and Sampling
In line-locked or genlocked applications, it is necessary to
know the exact phase relation of the output clock relative
to the input clock. Since the VCO is included within the
feedback loop in a simple PLL structure, the VCO output
is exactly phase aligned with the input clock. Every cycle
of the input clock equals NR/NF cycles of the VCO clock.
Figure 5: Simple PLL
Phase
Frequency
Detect
Feedback
Divider (N
F)
VCO
f
IN
f
OUT
Reference
Divider (N
R)
f
IN
f
OUT
The addition of a Post Divider, while adding flexibility,
makes the phase relation between the input and output
clock unknown because the Post Divider is outside the
feedback loop.
Figure 6: PLL with Post Divider
Phase
Frequency
Detect
Feedback
Divider (N
F)
VCO
f
IN
f
OUT
Reference
Divider (N
R)
f
IN
f
VCO
Post
Divider (N
F)
f
VCO
f
OUT
?
4.2.1
Clock Gobbler (Phase Adjust)
The Clock Gobbler circuit takes advantage of the un-
known relationship between input and output clocks to
permit the adjustment of the CLKP/CLKN output clock
phase relative to the REF input. The Clock Gobbler circuit
removes a VCO clock pulse before the pulse clocks the
Post Divider. In this way, the phase of the output clock
can be slipped until the output phase is aligned with the
input clock phase.
To adjust the phase relationship, switch the Feedback
Divider source to
the
Post Divider input via
the
FBKDSRC bit, and toggle the GBL register bit. The Clock
Gobbler output clock is delayed by one VCO clock period
for each transition of the GBL bit from zero to one.
4.2.2
Phase Alignment
To maintain a fixed phase relation between input and
output clocks, the Post Divider must be placed inside the
feedback loop. The source for the Feedback Divider is
obtained from the output of the Post Divider via the
FBKDSRC switch. In addition, the Feedback Divider must
be dividing at a multiple of the Post Divider.
Figure 7: Aligned I/O Phase
Phase
Frequency
Detect
Feedback
Divider (N
F)
VCO
f
IN
f
OUT
Reference
Divider (N
R)
Post
Divider (N
F)
f
IN
f
OUT
4.2.3
Phase Sampling and Initial Alignment
However, the ability to adjust the phase is useless with-
out knowing the initial relation between output and input
phase. To aid in the initial synchronization of the output
phase to input phase, a Phase Align “flag” makes a tran-
sition (zero to one or one to zero) when the output clock
phase becomes aligned with the feedback source phase.
The feedback source clock is, by definition, locked to the
input clock phase.
First, the FS6131 is used to sample the output clock with
the feedback source clock and set/clear the Phase Align
flag when the two clocks match to within a feedback
source clock period. Then, the Clock Gobbler is used to
delay the output phase relative to the input phase one
VCO clock at a time until a transition on the flag occurs.
When a transition occurs, the output and input clocks are
phase aligned.


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