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FS6131-01 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. FS6131-01
Description  Programmable Line Lock Clock Generator IC
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Maker  ETC1 [List of Unclassifed Manufacturers]
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FS6131-01 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

 
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FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
4.1.2
Feedback Divider
The Feedback Divider is based on a dual-modulus
prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the program-
mable Feedback Divider because of the high speeds at
which the VCO can operate. The dual-modulus technique
insures reliable operation at any speed that the VCO can
achieve and reduces the overall power consumption of
the divider.
For example, a fixed divide-by-eight could be used in the
Feedback Divider. Unfortunately, a divide-by-eight would
limit the effective modulus of the feedback divider path to
multiples of eight. The limitation would restrict the ability
of the PLL to achieve a desired input-frequency-to-
output-frequency ratio without making both the Reference
and Feedback Divider values comparatively large. Large
divider moduli are generally undesirable due to increased
phase jitter.
Figure 3: Feedback Divider
Dual-
Modulus
Prescaler
A
Counter
M
Counter
f
vco
To understand the operation, refer to Figure 3. The M-
counter (with a modulus of M) is cascaded with the dual-
modulus prescaler. If the prescaler modulus were fixed at
N, the overall modulus of the feedback divider chain
would be M
×N. However, the A-counter causes the
prescaler modulus to be altered to N+1 for the first A out-
puts of the prescaler. The A-counter then causes the
dual-modulus prescaler to revert to a modulus of N until
the M-counter reaches its terminal state and resets the
entire divider. The overall modulus can be expressed as
)
(
)
1
(
A
M
N
N
A
+
+
,
where M
≥ A, which simplifies to
A
N
M
+
×
.
4.1.3
Feedback Divider Programming
The requirement that M
≥A means that the Feedback Di-
vider can only be programmed for certain values below a
divider modulus of 56. The selection of divider values is
listed in Table 2.
If the desired Feedback Divider is less than 56, find the
divider value in the table. Follow the column up to find the
A-counter program value. Follow the row to the left to find
the M-counter value.
Above a modulus of 56, the Feedback Divider can be
programmed to any value up to 16383. See both Table 3
and Table 8 for additional programming information.
Table 2: Feedback Modulus Below 56
A-COUNTER: FBKDIV[2:0]
M-COUNTER:
FBKDIV[13:3]
000
001
010
011
100
101
110
111
00000000001
8
9
-----
-
00000000010
16
17
18
----
-
00000000011
24
25
26
27
-
-
-
-
00000000100
32
33
34
35
36
-
-
-
00000000101
40
41
42
43
44
45
-
-
00000000110
48
49
50
51
52
53
54
-
00000000111
56
57
58
59
60
61
62
63
FEEDBACK DIVIDER MODULUS
4.1.4
Post Divider
The Post Divider consists of three individually program-
mable dividers, as shown in Figure 4.
Figure 4: Post Divider
Post
Divider 1
(N
P1)
Post
Divider 2
(N
P2)
Post
Divider 3
(N
P3)
POST3[1:0]
POST2[1:0]
POST1[1:0]
POST DIVIDER (N
Px)
f
out
f
GBL
The moduli of the individual dividers are denoted as NP1,
NP2, and NP3, and together they make up the array
modulus NPx.
3
2
1
P
P
P
Px
N
N
N
N
×
×
=


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