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LM3503 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LM3503
Description  Dual-Display Constant Current LED Driver with Analog Brightness Control
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LM3503 Datasheet(HTML) 3 Page - National Semiconductor (TI)

 
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Pin Descriptions/Functions
Bump #
Pin #
Name
Description
A1
9
Cntrl
White LED Current Control Connection
B1
7
Fb
Feedback Voltage Connection
C1
6
V
OUT2
Drain Connections of the NMOS and PMOS Field Effect Transistor (FET) Switches
(Figure 1: N2 and P1). Connect 100nF at V
OUT2 node if VOUT2 is not used
D1
4
V
OUT1
Over-Voltage Protection (OVP) and Source Connection of the PMOS FET Switch
(Figure 1: P1)
D2
2 and 3
Sw
Drain Connection of the Power NMOS Switch (Figure 1: N1)
D3
15 and 16
Pgnd
Power Ground Connection
C3
14
Agnd
Analog Ground Connection
B3
13
V
IN
Input Voltage Connection
A3
12
En2
NMOS FET Switch Control Connection
A2
10
En1
PMOS FET Switch Control Connection
1
NC
No Connection
5
NC
No Connection
8
NC
No Connection
11
NC
No Connection
DAP
DAP
Die Attach Pad (DAP), to be soldered to the printed circuit board’s ground plane for
enhanced thermal dissipation.
Cntrl (Bump A1): White LED current control pin. Use this
pin to control the feedback voltage with an external DC
voltage. The feedback voltage is given as V
Fb = (0.156) *
(V
Cntrl) for the control voltage range of 0V
≤ V
Cntrl
≤ 3.5V.
Fb (Bump B1):Output voltage feedback connection.
V
OUT2 (Bump C1):Drain connections of the internal PMOS
and NMOS FET switches (Figure 1: P1 and N2). It is recom-
mended to connect 100nF at V
OUT2 if VOUT2 is not used for
LM3503-35V & LM3503-44V versions.
V
OUT1(Bump D1):
Source connection of the internal PMOS FET switch (Figure
1: P1) and OVP sensing node. The output capacitor must be
connected as close to the device as possible, between the
V
OUT1 pin and ground plane. Also connect the Schottky
diode as close as possible to the V
OUT1 pin to minimize trace
resistance and EMI radiation.
Sw (Bump D2):
Drain connection of the internal power NMOS FET switch
(Figure 1: N1). Minimize the metal trace length and maxi-
mize the metal trace width connected to this pin to reduce
EMI radiation and trace resistance.
Pgnd (Bump D3): Power ground pin. Connect directly to the
ground plane.
Agnd (Bump C3):Analog ground pin. Connect the analog
ground pin directly to the Pgnd pin.
V
IN (Bump B3): Input voltage connection pin. The CIN ca-
pacitor should be as close to the device as possible, be-
tween the V
IN pin and ground plane.
En2 (Bump A3): Enable pin for the internal NMOS FET
switch (Figure 1: N2) during device operation. When V
En2 is
≥ 1.4V, the internal NMOS FET switch turns off and the SUB
display is turned on. The En2 pin has an internal pull down
circuit, thus the internal NMOS FET switch is normally in the
on state of operation with the SUB display turned off. When
V
En2 is
≤ 0.3V, the internal NMOS FET switch turns on and
the SUB display is turned off. If both V
En1 and VEn2 are
0.3V the LM3503 will shutdown. If V
OUT2 is not used, En2
must be floating or grounded and En1 used to enable the
device.
En1 (Bump A2): Enable pin for the internal PMOS FET
switch (Figure 1: P1) during device operation. When V
En1 is
≤ 0.3V, the internal PMOS FET switch turns on and the MAIN
display is turned off. When V
En1 is
≥ 1.4V, the internal PMOS
FET switch turns off and the MAIN display is turned on. If
both V
En1 and VEn2 are
≤ 0.3V the LM3503 will shutdown.
The En1 pin has an internal pull down circuit, thus the
internal PMOS FET switch is normally in the on state of
operation with the MAIN display turned off. If V
OUT2 is not
used, En2 must be grounded and En1 use to enable the
device.
www.national.com
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