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CRD44130-FB Datasheet(PDF) 11 Page - Cirrus Logic |
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CRD44130-FB Datasheet(HTML) 11 Page - Cirrus Logic |
11 / 39 page DS690RD2 11 CRD44130-FB 2.4 Board Connections 2.4.1 Audio Inputs The CRD44130-FB provides stereo analog and digital inputs. The Analog inputs are J9 (left input) and J10 (right input). When analog inputs are used, full scale output is achieved when the analog input level is 2.0 Vrms. S/PDIF digital input can be either the optical receiver J8 or the RCA connector J11. When a valid PCM S/PDIF digital audio signal is present on J8 or J11 (cannot be present on both simultaneously), the CRD44130-FB outputs the program material present on that digital input. When a valid PCM S/PDIF digital audio signal is not present on either J8 or J11 (or both are mistakenly driven simultaneously), the CRD44130-FB outputs the program material present on its analog inputs. Due to the timing constraints of the FPGA, digital audio inputs must be limited to a sample rates of 32-96 kHz. 2.4.2 Speaker Outputs The CRD44130-FB provides speaker-level left, right, and low-frequency speaker outputs. Left and right channel output connections are made through speaker terminal J1; and the low-frequency speaker output connection is made through speaker terminal J2. Refer to Figure 4 for speaker connection details. When LED D14 is lit, this indicates that 2.1 is enabled. This means that the left, right, and low-frequency channels will be filtered according to the frequency response shown in Figure 14. In this mode, the low- frequency channel will be the filtered sum of the left and right channels. When 2.1 is disabled (by pressing push-button S1), the board provides no filtering and the low-frequency output produces full bandwidth left- channel audio. LFE- LFE+ R- R+ L- L+ J1 J2 Figure 4. Speaker Output Connections |
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