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MC54HC273A Datasheet(PDF) 3 Page - Motorola, Inc

Part No. MC54HC273A
Description  OCTAL D FLIP-FLOP WITH COMMON CLOCK AND RESET
Download  7 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC54HC273A Datasheet(HTML) 3 Page - Motorola, Inc

   
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MC54/74HC273A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Unit
v 125_C
v 85_C
– 55 to
25
_C
VCC
V
Test Conditions
Parameter
Symbol
VOL
Maximum Low–Level Output
Voltage
Vin = VIL
|Iout| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIL
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
IOZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
4.0
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Sb l
P
V
Guaranteed Limit
Ui
Symbol
Parameter
VCC
V
– 55 to
25
_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
15
30
35
5.0
10
24
28
4.0
8.0
20
24
MHz
tPLH
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
145
90
29
25
180
120
36
31
220
140
44
38
ns
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
145
90
29
25
180
120
36
31
220
140
44
38
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
C
P
Di
i
i
C
i
(P
E
bl d O
)*
Typical @ 25
°C, VCC = 5.0 V
F
CPD
Power Dissipation Capacitance (Per Enabled Output)*
48
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).


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