DS700DB1

5

CDB53L21

1.5

CS8406 Digital Audio Transmitter

A complete description of the CS8406 transmitter (Figure 29 on page 25) and a discussion of the digital au-

dio interface are included in the CS8406 data sheet.

The CS8406 converts the PCM data generated by the CS53L21 to the standard S/PDIF data stream and

routes this signal to the optical and RCA connectors. The CS8406 operates in slave mode only, accepting

either a 128xFs or 256xFs master clock, and can operate in either the Left-Justified or I²S interface format.

Selections are made in the control port of the FPGA, accessible through the “General Configurations” tab

of the Cirrus FlexGUI software or through the on-board switches, “FPGA H/W Control.” Section 2. “Software

Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.

1.6

Oscillator

The on-board oscillator provides one of the system master clocks. Selections are made in the control port

of the FPGA, accessible through the “General Configurations” tab of the Cirrus FlexGUI software or through

the on-board switches, “FPGA H/W Control.” Section 2. “Software Mode Control” on page 7 and Section 3.

“Hardware Mode Control” on page 13 provide configuration details.

The oscillator is mounted in pin sockets, allowing easy removal or replacement. Additional sockets are also

installed, allowing the optional use of a full- or half-can-sized oscillator.

1.7

I/O Stake Headers

The evaluation board has been designed to allow interfacing with external systems via a serial port header

(reference designation J5) and a control port header, “CS53L21 S/W Control.” The serial port header pro-

vides access to the serial audio signals required to interface with a DSP (Figure 31 on page 27). Selections

are made in the control port of the FPGA, accessible through the “General Configurations” tab of the Cirrus

FlexGUI software or through the on-board switches, “FPGA H/W Control.” Section 2. “Software Mode Con-

trol” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details.

moving all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable

to the “CONTROL” position, allowing operation of the CS53L21 in a user-application for system develop-

ment. A single “GND” row for the ribbon cable’s ground connection is provided to maintain signal integrity.

Two unpopulated pull-up resistors are also available should the user choose to use the CDB for the I²C pow-

er rail.

1.8

Analog Input

RCA connectors supply the line-level analog inputs through an AC-coupled passive filter. The signal from

these inputs may be driven to individual inputs or to all inputs of the CS53L21. A microphone may be con-

nected to one or both of the 1/8” jacks, MIC1 and MIC2.

To accommodate the microphone bias output available on certain input pins of the CS53L21, additional

stake headers are provided to MUX both the input audio signal and the output bias signal to or from the

CS53L21. Figure 28 on page 24 in the schematic set illustrates how signals are routed. Table 4 on page 21

provides more details for how to connect the jumpers. The CS53L21 data sheet details the required single-

ended signal amplitude that will drive the inputs to full scale.