Triscend A7S Configurable System-on-Chip Platform
SUBJECT TO CHANGE
86
TCH305-0001-002
Switching Between the PLL and the CLK Input Pin
1. If the current clock source is slower than 30 MHz, modify the memory interface timing
values to operate from the internal ring oscillator at the maximum oscillator frequency
of 30 MHz.
2. If using SDRAM and the current clock sources is faster than 15 MHz, modify the
SDRAM refresh timer for the internal ring oscillator’s minimum frequency of 15 MHz.
3. Write the CLK_SEL_BIT with ‘0’, switching temporarily to the internal ring oscillator.
4. If the CLK pin is the desired clock source, write a ‘0’ to the PLL_SEL_BIT. If the PLL
is the desired clock source, write a ‘1’ to the PLL_SEL_BIT.
5. If the new clock source is the PLL, modify the PLL parameters for the new desired
frequency.
a. Write a ‘1’ to the PLL_LOCK_CLEAR_BIT to reset the PLL Locked Flag.
b. Monitor the PLL_LOCK_BIT and wait for it to be set, indicating that the PLL is
locked to the specified frequency.
6. Switch back to the PLL or CLK input pin by writing a ‘1’ to the CLK_SEL_BIT.
7. Modify the memory interface and SDRAM timing values for the new clock source.
A
Alltte
errn
na
atte
e C
Cllo
oc
ck
k S
Siid
de
eb
ba
an
nd
d S
Siig
gn
na
all
The alternate clock sideband signal, ACLK, is only available to the CSL matrix and provides
the direct output from the 32.786 kHz crystal oscillator or the output from the PLL pre-scaler,
as shown in Figure 46.
The alternate clock signal, shown in Figure 48, is typically used during power-down mode
where a small “time-keeper” function in the CSL matrix operates directly from the 32.687 kHz
crystal oscillator and wakes the A7S device periodically.
ACLK
CSL
Alternate
Clock
Figure 48. The ACLK sideband signal drives directly and only into the CSL matrix.
C
Cllo
oc
ck
k a
an
nd
d P
PL
LL
L C
Co
on
nttrro
oll R
Re
eg
giis
stte
errs
s D
De
es
sc
crriip
pttiio
on
n
System control Memory Map
Address
Base
Offset
Register Name
Access
+ 0x00
Clock Control
R/W
+ 0x04
PLL Status
R
SYS_BASE
+ 0x08
PLL Status Clear
W
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