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TA7S04 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. TA7S04
Description  Triscend A7S Configurable System-on-Chip Platform
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Maker  ETC1 [List of Unclassifed Manufacturers]
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TA7S04 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

 
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Triscend A7S Configurable System-on-Chip Platform
SUBJECT TO CHANGE
4
TCH305-0001-002
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na
all IIn
ntte
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as
sh
h,, S
SD
DR
RA
AM
M
A static memory interface unit seamlessly connects the A7S device to external static
memories such as Flash or SRAM, as shown in Figure 2. An external Flash memory de-
vice contains the A7S’s initialization boot program plus the system application code. The
external memory interface has programmable read/write control and chip-select signals
that provide flexible set-up, strobe, and hold timing. The CPU connects directly to exter-
nal memory, eliminating any potential latency incurred by using the CSI bus. For low fre-
quency or minimal applications, the ARM7TDMI processor directly fetches its instructions
from external Flash.
The A7S optionally supports external SDRAM, offering additional affordable and high-
density memory to the system. The SDRAM interface connects an A7S-based system to
a variety of SDRAM types and configurations, including 100-pin DIMMs. The SDRAM in-
terface operates at up to 60 MHz and provides options to optimize the interface timing for
slower system clocks. SDRAM memory is ideal for DMA buffers. Similarly, the applica-
tion program can be stored in slow, cheap, byte-wide Flash and copied into SDRAM at
power-up. Then, the CPU starts executing code from the wider and faster SDRAM mem-
ory. The Flash and SDRAM interfaces share device pins, as shown in Figure 2.
Triscend A7
Configurable
System-on-Chip
(CSoC)
JTAG Connector
TCK TMS
TDI
TDO
TCK TMS
TDI
TDO
XIN
XOUT
RST-
SLAVE-
VCCIO
VCCIO
PIO[xxx:0]
FLASH
1Mx8
CE-
WE-
OE-
A[19:0]
D[7:0]
CE0-
WE-
OE-
SDCE0-
SDCLK
SDCKE
D[7:0]
D[15:8]
D[23:16]
D[31:24]
A[19:0]
A[23:20]
A[31:24]
[1]
[0]
[0]
[1]
[3:2]
[5:4]
[7:6]
[7:6]
[18:8]
[18:8]
CSoC Initialization Data
Application Code Storage
Faster Code Fetch Store
Application Data Storage
SDRAM
4Mx16
RAS
CAS
CLK
CKE
BS[1:0]
DQM[1:0]
WE-
CE-
A[10:0]
DQ[15:0]
SDRAM
4Mx16
RAS
CAS
CLK
CKE
BS[1:0]
DQM[1:0]
WE-
CE-
A[10:0]
DQ[15:0]
32.768 kHz
(OPTIONAL)
(OPTIONAL)
VCCPLL
+2.5V
VCCIO
+2.5V
or
+3.3V
VSYS
To ext.
memory
supply
VCC
+2.5V
GNDPLL
GNDIO
GND
Figure 2. A typical A7S-based system.


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