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TA7S04 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. TA7S04
Description  Triscend A7S Configurable System-on-Chip Platform
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Maker  ETC1 [List of Unclassifed Manufacturers]
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TA7S04 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

 
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TCH305-0001-002
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SUBJECT TO CHANGE
System Overview
The Triscend A7S Configurable System-on-Chip (CSoC) device is a complete, high-
performance user-programmable system. The A7S contains
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an embedded 32-bit ARM7TDMI RISC processor
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a next generation embedded programmable logic architecture, optimized for processor
and bus interface
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a high-performance 32-bit internal bus supporting up to 455Mbytes per second peak
transfer rates
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16Kbytes of internal scratchpad SRAM memory and a separate 8Kbyte cache.
The ARM7TDMI is a general-purpose 32-bit RISC microprocessor that supports the com-
plete ARM 32-bit instruction set and the reduced 16-bit instruction set, referred to as
Thumb. The ARM7TDMI processor offers the following advantages:
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High-performance for very low power consumption and price
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Excellent code density using the Thumb instruction set
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Low-latency interrupt response
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The processor is paired with an 8Kbyte unified code/data cache and a 16Kbyte (4Kx32)
scratchpad RAM for storing timing critical code or data. The scratchpad is accessible over
the Configurable System Interconnect (CSI) bus by other CSI bus masters, primarily for
DMA transfers. The ARM processor is integrated with other system components and the
Configurable System Logic (CSL) matrix to provide a complete configurable system, as il-
lustrated in Figure 1.
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The embedded SRAM-based Configurable System Logic (CSL) matrix provides full, easy-
to-use system customization. The high-performance programmable logic architecture
consists of a highly interconnected matrix of CSL cells. Resources within the matrix pro-
vide seamless access to and from the internal CSI bus. Each CSL cell performs various
potential functions, including combinatorial and sequential logic. The combinatorial por-
tion performs Boolean logic operations, arithmetic functions, and memory. The sequential
element performs independently or in tandem with the combinatorial function. The abun-
dant programmable input/output blocks (PIOs) provide a highly flexible interface between
external functions and the internal system bus or configurable system logic. Each PIO of-
fers advanced I/O capabilities including selectable output drive current, optional input hys-
teresis, and programmable low-power functionality during power-down mode.
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A high-performance internal system bus—called the Configurable System Interconnect
(CSI) bus— interconnects the embedded processor, its peripherals, and the CSL matrix at
a maximum speed of 60MHz. The bus simultaneously provides 32 bits of read data, 32
bits of write data, and a 32-bit address. Multiple bus masters arbitrate for bus access.
Potential bus masters include the ARM7TDMI processor, the read and write channels of
all four DMA channels, and the JTAG interface. CSL-based devices become CSI bus
masters using DMA services. The CSI bus and the local CPU bus following the little en-
dian format.


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