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TAS5508BPAGR Datasheet(PDF) 74 Page - Texas Instruments |
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TAS5508BPAGR Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 106 page  www.ti.com 7 Serial-Control Interface Register Definitions 7.1 Clock Control Register (0x00) 7.2 General Status Register 0 (0x01) 7.3 System Control Register 1 (0x03) TAS5508B 8-Channel Digital Audio PWM Processor SLES162B – DECEMBER 2005 – REVISED APRIL 2006 Unless otherwise noted, the I2C register default values are in bold font. Note that u indicates unused bits. Bit D1 is don't care. Table 7-1. Clock Control Register Format D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 – – – – 32-kHz data rate 0 0 1 – – – – 38-kHz data rate 0 1 0 – – – – 44.1-kHz data rate 0 1 1 – – – – 48-kHz data rate 1 0 0 – – – – 88.2-kHz data rate 1 0 1 – – – – 96-kHz data rate 1 1 0 – – – – 176.4-kHz data rate 1 1 1 – – – – 192-kHz data rate – – – 0 0 0 MCLK frequency = 64 – – – 0 0 1 MCLK frequency = 128 – – – 0 1 0 MCLK frequency = 192 – – – 0 1 1 MCLK frequency = 256 – – – 1 0 0 MCLK frequency = 384 – – – 1 0 1 MCLK frequency = 512 – – – 1 1 0 MCLK frequency = 768 – – – 1 1 1 Reserved – – – – – – 1 Clock register is valid (read-only) – – – – – – 0 Clock register is not valid (read-only) Table 7-2. General Status Register Format D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 1 – – – – – – – Clip indicator – – 0 0 0 0 1 1 Identification code for TAS5508B Bits D6, D5, D2, D1, and D0 are don't care. Table 7-3. System Control Register-1 Format D7 D6 D5 D4 D3 D2 D1 D0 Function 0 – – PWM high pass disabled 1 – – PWM high pass enabled – 0 – Soft unmute on recovery from clock error – 1 – Hard unmute on recovery from clock error – – 1 PSVC Hi-Z enabled – – 0 PSVC Hi-Z disabled Serial-Control Interface Register Definitions 74 |
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