M37151M8-XXXFP datasheet(67/139 Pages) RENESAS

Part #	M37151M8-XXXFP

Description	SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP

MITSUBISHI MICROCOMPUTERS

66

Rev. 1.0

The vertical display start position is determined by counting the hori-

zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are

positive polarity (negative polarity), the count starts at the rising edge

(falling edge) of HSYNC signal after the fixed cycle of the rising edge

(falling edge) of VSYNC signal. So the interval from the rising edge

(falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC

signal needs enough time (2 machine cycles or more) to avoid jitters.

The polarity of HSYNC and VSYNC signals can be select with the I/O

polarity control register (address 00D816).

Fig. 8.11.6 Supplement Explanation for Display Position

When bits 0 and 1 of the I/O polarity control register

(address 00D816) are set to “1” (negative polarity)

VSYNC signal input

VSYNC control

signal in

microcomputer

0.25 to 0.50 [

µs]

( at f(XIN) = 8MHz)

Period of counting

HSYNC signal

(See note 2)

HSYNC

signal input

Not count

12345

Notes 1 : The vertical position is determined by counting falling edge of HSYNC

signal after rising edge of VSYNC control signal in the microcomputer.

2 : Do not generate falling edge of HSYNC signal near rising edge of

VSYNC control signal in microcomputer to avoid jitter.

3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or

more.

8 machine cycles

or more

8 machine cycles

or more

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M37151M8-XXXFP Datasheet(PDF) 67 Page - Renesas Technology Corp

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