M37151 datasheet(72/139 Pages) RENESAS | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

Part #	M37151

Description	SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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Manufacturer	RENESAS [Renesas Technology Corp]

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS

M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP

71

Rev. 1.0

8.11.4 Field Determination Display

When displaying a block with vertical dot size of 1/2H, the differ-

ences in the synchronizing signal waveform of the interlacing system

determine whether the field is odd or even. The dot lines 0 and 1

(refer to Figure 8.11.15), corresponding to each field, are displayed

alternately.

In the following, the field determination standard for the case where

both the horizontal sync signal and the vertical sync signal are nega-

tive-polarity inputs will be explained. A field determination is deter-

mined by detecting the time from a falling edge of the horizontal sync

signal until a falling edge of the VSYNC control signal (refer to Figure

8.11.6) in the microcomputer and then comparing this time with the

time of the previous field. When the time is longer than the previous

time, it is regarded as an even field. When the time is shorter, it is

regarded as an odd field

The contents of this field can be read out by the field determination

flag (bit 6 of the I/O polarity control register at address 00D816). A dot

line is specified by bit 5 of the I/O polarity control register (refer to

Figure 8.11.15).

However, the field determination flag read out from the CPU is fixed

to “0” for even fields or “1” for odd fields, regardless of bit 5.

Fig. 8.11.14 I/O Polarity Control Register

0

0 : “

” at even field

“

” at odd field

1 : “

” at even field

“

” at odd field

b7 b6 b5 b4 b3 b2 b1 b0

I/O polarity control register (PC) [Address 00D8 16]

B

Name

Functions

After reset R W

I/O Polarity Control Register

0HSYNC input polarity

switch bit (PC0)

0 : Positive polarity input

1 : Negative polarity input

0

1

0 : Positive polarity input

1 : Negative polarity input

0

2

R, G, B output polarity

switch bit (PC2)

0 : Positive polarity output

1 : Negative polarity output

0

3

OUT1 output polarity

switch bit (PC3)

0 : Positive polarity output

1 : Negative polarity output

0

5

Display dot line selection

bit (PC5) (See note)

0

6

Field determination flag

(PC6)

0 : Even field

1 : Odd field

1

4, 7

0

VSYNC input polarity

switch bit (PC1)

RW

R —

RW

Fix these bits to “0.”

Note: Refer to the corresponding figure. 8.11.15

0

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