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M37151 Datasheet(PDF) 38 Page - Renesas Technology Corp

Part No. M37151
Description  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M37151 Datasheet(HTML) 38 Page - Renesas Technology Corp

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
37
Rev. 1.0
8.6.6 START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
is output for 1 byte. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.10 for the START condition
generation timing diagram, and Table 8.6.2 for the START condition/
STOP condition generation timing table.
Fig. 8.6.10 START Condition Generation Timing Diagram
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
BB flag
Set time
for BB flag
8.6.7 STOP Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
to set the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP
condition will then be generated. The STOP condition generation tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 8.6.11 for the
STOP condition generation timing diagram, and Table 8.6.2 for the
START condition/STOP condition generation timing table.
Fig. 8.6.11 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Setup time
(START condition)
Setup time
(STOP condition)
Hold time
Set/reset time
for BB flag
Standard Clock Mode
5.0
µs (20 cycles)
4.25
µs (17 cycles)
5.0
µs (20 cycles)
3.0
µs (12 cycles)
High-speed Clock Mode
2.5
µs (10 cycles)
1.75
µs (7 cycles)
2.5
µs (10 cycles)
1.5
µs (6 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
BB flag
Reset time
for BB flag


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