Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07053 Rev. **
05/03/01
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 2 of 18
http://www.cypress.com
APPROVED PRODUCT
C9812
Pin Description
PIN No.
Pin Name
PWR
I/O
TYPE
Description
1
SEL2/REF
VDD
I/O
3.3V 14.318 MHz clock output.
This pin also serves as the select strap (associates with SEL0 &
1, see app. note page 5) for clock frequencies during power up.
Refer to Table 1 for detail. This pin has an internal pull-down
(Typ. 70K
Ω).
3
XIN
VDD
I
OSC1
14.318MHz Crystal input
4
XOUT
VDD
O
14.318MHz Crystal output
11, 12, 13,
15, 16, 18,
19, 20
PCI0/ICH
PCI(1..7)
VDD
O
3.3V PCI clock outputs
7, 8
3V66(0,1)
VDD
O
3.3V Fixed 66.6 MHz clock outputs
25
USB
VDD
O
3.3V Fixed 48 MHz clock outputs
26
DOT
VDD
O
3.3V Fixed 48 MHz clock outputs
28, 29
SEL(0,1)
VDD
I
3.3V LVTTL compatible inputs for logic selection. Has an
internal pull-up (Typ. 250K
Ω)
30
SDATA
VDD
I
I²C compatible SDATA input. Has an internal pull-up (>100K
Ω)
31
SCLK
VDD
I
I²C compatible SCLK input. Has an internal pull-up (>100K
Ω)
32
PD#
VDD
I
3.3V LVTTL compatible input. Device enters powerdown mode
When held LOW. Has an internal pull-up (>100K
Ω)
34
DCLK
VDD
O
3.3V output running 100MHz
36, 37, 39,
40, 42, 43,
45, 46
SDRAM(7..0)
VDDS
O
3.3V output running 100MHz. All SDRAM outputs can be turned
off through SMBUS.
49, 50, 52
CPU(2)_ITP,
CPU(1,0)
VDDC
O
2.5V Host bus clock outputs. 66, 100 or 133MHz depending on
state of SEL(2..0)
54, 55
IOAPIC(1,0)
VDDI
O
2.5V clock outputs running rising edge synchronous with the
PCI clock.
2, 9, 10, 21,
27, 33
VDD
-
3.3V Power Supply
22
VDDA
-
Analog circuitry 3.3V Power Supply
23
VSSA
-
Analog circuitry power supply Ground pins.
51, 53
VDDC, VDDI
-
2.5V Power Supply’s
5, 6,14, 17,
24, 35, 41,
47, 48, 56
VSS
-
-
Common Ground pins.
38, 44
VDDS
-
-
3.3V power support for SDRAM clock output drivers.
A bypass capacitor (0.1
µµµµF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
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