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BGY284 Datasheet(PDF) 6 Page - NXP Semiconductors

Part No. BGY284
Description  Power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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BGY284 Datasheet(HTML) 6 Page - NXP Semiconductors

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2003 Aug 20
6
Philips Semiconductors
Preliminary specification
power amplifier with integrated control loop for
GSM850, EGSM900, DCS1800 & PCS1900
BGY284
TIMING DIAGRAM
10 µs
P
L LB,HB
V
DAC
P
D LB,HB
Vband
VTXon
VSTAB
(*)
-30
(***)
dB
+1
-1
(**)
-6
+4
10 µs
10 µs
8 µs
8 µs
10 µs
7056/13 (542.8) µs
(147 bits)
t
Fig.3 Timing diagram
TIMING CHARACTERISTICS
ZS =ZL =50 Ω; −3 ≤ PD HB,LB ≤ 3dBm; 3.1 ≤ VBAT ≤ 4.6 V; 2.6 ≤ VSTAB ≤ 3.0 V; −20 ≤ Tmb ≤ 85 °C; 1 : 8 ≤δ≤ 4: 8;
unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
td1
delay time; VSTAB high voltage input power before transition VTXon to
logic 1
0
−−
µs
td2
delay time; Vband to logic 0 or logic 1 before VTXon transition to logic 1
0
−−
µs
td3
delay time; RF signal on RFin HB,LB before VDAC ramp
0
−−
µs
td4
delay time; voltage step on VDAC after transition VTXon to logic 1
10
−−
µs
td5
delay time; transition of VTXon to logic 0 after VDAC signal to off
0
−−
µs
td6
delay time; VSTAB to 0, after VTXon to logic 0
10
−−
µs
td7
delay time; change of Vband after VTXon to logic 0
0
−−
µs
td8
delay time; removal of RF signal on RFin HB,LB after VDAC signal to off
0
−−
µs


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