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DS26102 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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DS26102 Datasheet(HTML) 5 Page - Maxim Integrated Products |
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5 / 64 page  DS26102 16-Port TDM-to-ATM PHY 5 of 64 1. FEATURES § Supports 16 T1/E1 Ports § Supports Fractional T1/E1 and Arbitrary Bit Rates in Multiples of 64kbps (DS0/TS) Up to 2.048Mbps § Supports Clear E1 § Compliant to the ATM Forum Specifications for ATM Over T1 and E1 § Standard UTOPIA II Interface to the ATM Layer § Configurable UTOPIA Address Range § Generic 8-Bit Asynchronous Microprocessor Interface for Configuration and Status Indications Including Interrupt Capability § Physical Layer Interface Can Accept T1/E1 TDM Stream in the Form of Either (1) Clock, Data, and Frame-Overhead Indication or (2) Gapped Clock (Gapped at Overhead Positions in the Frame) and Data § Selectable Active Clock Edge for Interface with the T1/E1 Framer § Supports Diagnostic Loopback § Optional Payload Scrambling in Transmit Direction and Descrambling in Receive Direction as per the ITU I.432 for the Cell-Based Physical Layer § Optional HEC Insertion in Transmit Direction with Programmable COSET Polynomial Addition § Option of Using Either Idle or Unassigned Cells for Cell-Rate Decoupling in Transmit Direction § 1-Byte Programmable Pattern for Payload of Cells Used for Cell-Rate Decoupling § Tx FIFO Depth Configurable to Either 2, 3, or 4 Cells § Transmit FIFO Depth Indication for 2-Cell Space Through External Pins § Optional Single-Bit HEC Error Insertion § HEC-Based Cell Delineation as per I.432 § Optional Single-Bit HEC Error Correction in the Receive Direction § Optional Filtering of HEC-Errored Cells Received § Optional Receive Idle/Unassigned Cell Filtering § Optional User-Defined Cell Filtering Based on Programmable Header Bits § Programmable Loss-Of-Cell Delineation (LCD) Integration and Interrupt § Interrupt for FIFO Overrun in Receive Direction § Saturating Counts for (1) Number of Error-Free Assigned Cells Received and Transmitted and (2) Number of Correctable and Uncorrectable HEC-Errored Cells Received § Selectable Internally Generated Clock (System Clock Divided by 8) in Diagnostic Loopback Mode § Integrated PLL Generates High-Frequency Clocks § IEEE 1149.1 JTAG Boundary Scan Support 2. APPLICABLE STANDARDS [1] ATM Forum “DS1 Physical Layer Specification,” af-phy-0016.000, September 1994 [2] ATM Forum “E1 Physical Layer Specification,” af-phy-0064.000, September 1996 [3] ATM Forum “UTOPIA Level 2 Specification,” Version 1.0, af-phy-0039.000, June 1995 [4] B-ISDN User-Network Interface—Physical Layer Specification—ITU-T Recommendation I.432—3/93 |
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