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CLC031 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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CLC031 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 31 page  Required Input Conditions (Continued) Symbol Parameter Conditions Reference Min Typ Max Units f ACLK Ancilliary / Control Data Clock Frequency A CLK 74.25 MHz DC ACLK Ancilliary / Control Clock Duty Cycle 45 50 55 % t r,tf Ancilliary / Control Clock and Data Rise Time, Fall Time 10%–90% 1.0 1.5 3.0 ns t S Setup Time, AD N to ACLK or IO N to ACLK Rising Edge Control Data Input or I/O Bus Input IO N,ADN,ACLK Timing Diagram 3.0 1.5 ns t H Hold Time, Rising Edge A CLK to ADN or ACLK to IO N 3.0 1.5 ns R REF Bias Supply Reference Resistor Tolerance 1% 4.75k Ω f EXT CLK External Clock Frequency Ext Clk −100 ppm 27.0 +100 ppm MHz f XTAL Crystal Frequency Figure 6 XTALo, XTALi DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units V IH Input Voltage High Level All LVCMOS Inputs 2.0 V DDIO V V IL Input Voltage Low Level V SSIO 0.8 I IH Input Current High Level V IH =VDDIO(Note 8) +85 +150 µA I IL Input Current Low Level V IL =VSSIO −1 −20 V OH Output Voltage High Level I OH =−2 mA All LVCMOS Outputs 2.4 2.7 V DDIO V V OL Output Voltage Low Level I OL =+2 mA V SSIO V SSIO +0.3 V SSIO +0.5V V OHV Minimum Dynamic V OH I OH =−2 mA (Note 6) V DDIO −0.5 V OLP Maximum Dynamic V OL I OL =+2 mA (Note 6) V SSIO +0.4 V SDI Serial Data Input Voltage SDI, SDI 100 800 880 mV P-P I SDI Serial Data Input Current ±1 ±10 µA V TH Input Thereshold Over VCM range <50 mV I BB Bias Supply Output Current R BB = 6.19k Ω 1% 188 220 µA I REF Reference Output Current R REF = 4.75k Ω 1% 262 290 I DD (3.3V) Power Supply Current, 3.3V Supply, Total 270M BPS Data Rate V DDIO,VDDSI 31.0 45.0 mA 1,485M BPS Data Rate 35.0 50.0 I DD (2.5V) Power Supply Current, 2.5V Supply, Total 270M BPS Data Rate V DDD,VDDPLL 76 115 mA 1,485M BPS Data Rate 210 325 www.national.com 6 |
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