AD9923A datasheet(68/88 Pages) AD

Part #	AD9923A

Description	CCD Signal Processor with V-Driver and Precision Timing??Generator

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AD9923A

Rev. 0 | Page 68 of 88

UPDATING NEW REGISTER VALUES

The AD9923A internal registers are updated at different times,

depending on the particular register. Table 44 summarizes the

four types of register updates. The register listing (Table 45

through Table 57) also contain a column with update type to

identify when each register is updated:

•

SCK Updated

—Some registers are updated when the 28th

data bit (D27) is written. These registers are used for

functions, such as power-up and reset, that do not require

gating with the next VD boundary.

•

VD Updated

—Many of the registers are updated at the

next VD falling edge. By updating these values at the next

VD edge, the current field is not corrupted, and the new

register values are applied to the next field. The VD update

can be further delayed, past the VD falling edge, by using

the UPDATE register (Address 0x18). This delays the

VD-updated register updates to any desired HD line in the

field. Note that the field registers are not affected by the

UPDATE register.

•

SG Updated

—A few shutter registers are updated at the

HD falling edge at the end of an SG active line. These

registers control the SUBCK signal; therefore, the SUBCK

output is not updated until the SG line is complete.

•

SCP Updated

—All V-pattern and V-sequence registers are

updated at the next SCP where they will be used. For

example, in Figure 88, this field has selected Region 1 to

use V-Sequence 3 for the vertical outputs; therefore, a write

to a V-Sequence 3 or V-pattern group register, which is

referenced by V-Sequence 3, is updated at SCP 1. If there

are multiple writes to the same register, only the last one

before SCP1 is updated. Likewise, a register write to a

V-Sequence 5 register is updated at SCP 2, and a register

write to a V-Sequence 8 register is updated at SCP 3.

Table 44. Register Update Locations

Update

Type

Description

SCK

Register is immediately updated when the 28th data

bit (D27) is written.

VD

Register is updated at the VD falling edge. VD

updated registers can be delayed further by using the

UPDATE register at Address 0x18. Field registers are

not affected by the UPDATE register.

SG

Register is updated at the HD falling edge at the end

of the SG active line.

SCP

Register is updated at the next SCP when the register

is used.

VD

REGION 0

HD

SCP 1

SCP 2

SCP 3

REGION 1

REGION 2

REGION 3

VSG

SGLINE

SCP 0

SERIAL

WRITE

SCK

UPDATED

SCP 0

VD

UPDATED

SG

UPDATED

SCP

UPDATED

V1A TO V10

USE VSEQ2

USE VSEQ3

USE VSEQ5

USE VSEQ8

Figure 88. Register Update Locations (See Table 44 for Definitions)

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