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AD9923A Datasheet(PDF) 6 Page - Analog Devices

Part No. AD9923A
Description  CCD Signal Processor with V-Driver and Precision Timing™ Generator
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD9923A Datasheet(HTML) 6 Page - Analog Devices

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AD9923A
Rev. 0 | Page 6 of 88
Parameter
Conditions/Comments
Min
Typ
Max
Unit
BLACK LEVEL CLAMP
Measured at ADC output
Clamp Level Resolution
1024
Steps
Minimum Clamp Level (Code 0)
0
LSB
Maximum Clamp Level (Code 1023)
255
LSB
ANALOG-TO-DIGITAL CONVERTER (ADC)
Resolution
12
Bits
Differential Nonlinearity (DNL)
−1.0
±0.5
+1.0
LSB
No Missing Codes
Guaranteed
Full-Scale Input Voltage
2.0
V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
V
Reference Bottom Voltage (REFB)
1.0
V
SYSTEM PERFORMANCE
Includes entire signal chain
Gain Accuracy
Low Gain (VGA Code 15)
Default CDS gain (0 dB)
6.0
6.5
7.0
dB
Maximum Gain (VGA Code 1023)
42.0
42.5
43.0
dB
Peak Nonlinearity, 500 mV Input Signal
12 dB gain applied
0.1
%
Total Output Noise
AC-grounded input, 6 dB gain applied
1.0
LSB rms
Power Supply Rejection (PSR)
Measured with step change on supply
50
dB
1 Input signal characteristics are defined as shown in Figure 3.
200mV MAX
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V MAX
INPUT SIGNAL RANGE
(0dB CDS GAIN)
Figure 3. Signal Characteristics
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.
Table 6.
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
MASTER CLOCK, CLI
CLI Clock Period
tCONV
27.8
ns
CLI High/Low Pulse Width
11.2
13.9
16.6
ns
Delay from CLI Rising Edge to Internal Pixel Position 0
tCLIDLY
6
ns
AFE CLPOB Pulse Width1, 2
2
20
Pixels
Allowable Region for HD Falling Edge to CLI Rising Edge
Only valid in slave mode
tHDCLI
4
tCONV − 2
ns
SHP Inhibit Region
Only valid in slave mode
tSHPINH
30
39
Edge location
AFE SAMPLE LOCATION1
SHP Sample Edge to SHD Sample Edge
tS1
11.6
13.9
ns
DATA OUTPUTS
Output Delay from DCLK Rising Edge1
tOD
8
ns
Inhibited Area for DOUTPHASE Edge Location
SHD
SHD + 11
Edge location
Pipeline Delay from SHP/SHD Sampling to Data Output
16
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
fSCLK
36
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tDV
10
ns
1 Parameter is programmable.
2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.


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