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AD9513BCPZ-REEL7 Datasheet(PDF) 20 Page - Analog Devices |
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AD9513BCPZ-REEL7 Datasheet(HTML) 20 Page - Analog Devices |
20 / 28 page AD9513 Rev. 0 | Page 20 of 28 Table 16. OUT0 Divide or OUT2 Divide S9 S10 OUT0 Divide (Duty Cycle1) S2 ≠ 2/3 OUT2 Divide (Duty Cycle1) S2 = 2/3 0 0 1 7 (43%) 1/3 0 2 (50%) 11 (45%) 2/3 0 3 (33%) 13 (46%) 1 0 4 (50%) 14 (50%) 0 1/3 5 (40%) 17 (47%) 1/3 1/3 6 (50%) 19 (47%) 2/3 1/3 8 (50%) 20 (50%) 1 1/3 9 (44%) 21 (48%) 0 2/3 10 (50%) 22 (50%) 1/3 2/3 12 (50%) 23 (48%) 2/3 2/3 15 (47%) 25 (48%) 1 2/3 16 (50%) 26 (50%) 0 1 18 (50%) 27 (48%) 1/3 1 24 (50%) 28 (50%) 2/3 1 30 (50%) 29 (48%) 1 1 32 (50%) 31 (48%) 1 Duty cycle is the clock signal high time divided by the total period. DIVIDER PHASE OFFSET The phase offset of OUT1 and OUT2 can be selected (see Table 13 to Table 15). This allows the relative phase of the outputs to be set. After a SYNC operation (see the Synchronization section), the phase offset word of each divider determines the number of input clock (CLK) cycles to wait before initiating a clock output edge. By giving each divider a different phase offset, output-to- output delays can be set in increments of the fast clock period, tCLK. Figure 24 shows four cases, each with the divider set to divide = 4. By incrementing the phase offset from 0 to 3, the output is offset from the initial edge by a multiple of tCLK. 01 4 123 5 9 67 8 10 14 11 12 13 5 tCLK CLOCK INPUT CLK DIVIDER OUTPUT DIV = 4 PHASE = 0 PHASE = 1 PHASE = 2 PHASE = 3 tCLK 2 × tCLK 3 × tCLK Figure 24. Phase Offset—Divider Set for Divide = 4, Phase Set from 0 to 2 For example: CLK = 491.52 MHz tCLK = 1/491.52 = 2.0345 ns For Divide = 4: Phase Offset 0 = 0 ns Phase Offset 1 = 2.0345 ns Phase Offset 2 = 4.069 ns Phase Offset 3 = 6.104 ns The outputs can also be described as: Phase Offset 0 = 0° Phase Offset 1 = 90° Phase Offset 2 = 180° Phase Offset 3 = 270° Setting the phase offset to Phase = 4 results in the same relative phase as Phase = 0° or 360°. The resolution of the phase offset is set by the fast clock period (tCLK) at CLK. The maximum unique phase offset is less than the divide ratio, up to a phase offset of 15. Phase offsets can be related to degrees by calculating the phase step for a particular divide ratio: Phase Step = 360°/Divide Ratio Using some of the same examples: Divide = 4 Phase Step = 360°/4 = 90° Unique Phase Offsets in Degrees Are Phase = 0°, 90°, 180°, 270° Divide = 9 Phase Step = 360°/9 = 40° Unique Phase Offsets in Degrees Are Phase = 0°, 40°, 80°, 120°, 160°, 200°, 240°, 280°, 320° |
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