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AD9481 Datasheet(PDF) 6 Page - Analog Devices

Part No. AD9481
Description  8-Bit, 250 MSPS 3.3 V A/D Converter
Download  28 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD9481 Datasheet(HTML) 6 Page - Analog Devices

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AD9481
Rev. 0 | Page 6 of 28
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted.
Table 4.
AD9481-250
Parameter
Temp
Test Level
Min
Typ
Max
Unit
CLOCK
Maximum Conversion Rate
Full
VI
250
MSPS
Minimum Conversion Rate
Full
IV
20
MSPS
Clock Pulse-Width High (tEH)
Full
IV
1.2
2
ns
Clock Pulse-Width Low (tEL)
Full
IV
1.2
2
ns
DS Input Setup Time (tSDS)
Full
IV
0.5
ns
DS Input Hold Time (tHDS)
Full
IV
0.5
ns
OUTPUT PARAMETERS1
Valid Time (tV)2
Full
VI
2.5
ns
Propagation Delay (tPD)
Full
VI
4
5.4
ns
Rise Time (tR) 10% to 90%
Full
V
670
ps
Fall Time (tF) 10% to 90%
Full
V
360
ps
DCO Propagation Delay (tCPD) 3
Full
VI
2.5
3.9
5.3
ns
Data-to-DCO Skew (tPD − tCPD)4
Full
VI
−0.5
+0.5
ns
A Port Data to DCO− Rising (tSKA)5
Full
IV
4
ns
B Port Data to DCO+ Rising (tSKB)
Full
IV
4
ns
Pipeline Latency (A, B)
Full
IV
8
Cycles
APERTURE
Aperture Delay (tA)
25°C
V
1.5
ns
Aperture Uncertainty (Jitter)
25°C
V
0.25
ps rms
OUT-OF-RANGE RECOVERY TIME
25°C
V
1
Cycle
1 CLOAD equals 5 pF maximum for all output switching specifications.
2 Valid time is approximately equal to minimum tPD.
3 TCPD equals clock rising edge to DCO (+ or −) rising edge delay.
4 Data changing to (DCO+ or DCO−) rising edge delay.
5 TSKA, TSKB are both clock rate dependent delays equal to TCYCLE − (Data to DCO skew).


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