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AD9461 Datasheet(PDF) 3 Page - Analog Devices

Part No. AD9461
Description  16-Bit, 130 MSPS IF Sampling ADC
Download  28 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD9461 Datasheet(HTML) 3 Page - Analog Devices

 
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AD9461
Rev. 0 | Page 3 of 28
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, SFDR = AGND, unless otherwise noted.
Table 1.
AD9461BSVZ
Parameter
Temp
Min
Typ
Max
Unit
RESOLUTION
Full
16
Bits
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
Full
−4.2
±0.1
+4.2
mV
Gain Error
25°C
−3
±0.5
+3
% FSR
Full
−3.4
+3.4
% FSR
Differential Nonlinearity (DNL)1
25°C
−1.0
±0.6
+1.0
LSB
Full
−1.0
+1.3
LSB
Integral Nonlinearity (INL)1
25°C
7
±5.0
+7
LSB
VOLTAGE REFERENCE
Output Voltage VREF = 1.7 V
Full
+1.7
V
Load Regulation @ 1.0 mA
Full
±2
mV
Reference Input Current (External VREF = 1.7 V)
Full
350
μA
INPUT REFERRED NOISE
25°C
2.6
LSB rms
ANALOG INPUT
Input Span
VREF = 1.7 V
Full
3.4
V p-p
VREF = 1.0 V
Full
2.0
V p-p
Internal Input Common-Mode Voltage
Full
3.5
V
External Input Common-Mode Voltage
Full
3.2
3.9
V
Input Resistance2
Full
1
Input Capacitance2
Full
6
pF
POWER SUPPLIES
Supply Voltage
AVDD1
Full
3.14
3.3
3.46
V
AVDD2
Full
4.75
5.0
5.25
V
DRVDD—LVDS Outputs
Full
3.0
3.6
V
DRVDD—CMOS Outputs
Full
3.0
3.3
3.6
V
Supply Current1
AVDD1
Full
405
426
mA
AVDD21, 3
Full
131
143
mA
IDRVDD1—LVDS Outputs
Full
72
81
mA
IDRVDD1—CMOS Outputs
Full
14
mA
PSRR
Offset
Full
1
mV/V
Gain
Full
0.2
%/V
POWER CONSUMPTION
LVDS Outputs
Full
2.2
2.4
W
CMOS Outputs (DC Input)
Full
2.0
W
1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3 For SFDR = AVDD1, IAVDD2 decreases by ~8 mA, decreasing power dissipation.


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