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AD9461 Datasheet(PDF) 1 Page - Analog Devices

Part No. AD9461
Description  16-Bit, 130 MSPS IF Sampling ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD9461 Datasheet(HTML) 1 Page - Analog Devices

 
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16-Bit, 130 MSPS IF Sampling ADC
AD9461
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
FEATURES
130 MSPS guaranteed sampling rate
78.7 dBFS SNR/90 dBc SFDR with 10 MHz input
(3.4 V p-p input, 130 MSPS)
77.7 dBFS SNR with 170.3 MHz input
(4.0 V p-p input, 130 MSPS)
77.0 dBFS SNR/84 dBc SFDR with 170 MHz input
(3.4 V p-p input, 130 MSPS)
76.3 dBFS SNR/86 dBc SFDR with 225 MHz input
(3.4 V p-p input, 125 MSPS)
89 dBFS two-tone SFDR with 169 MHz and 170 MHz
(130 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = ±0.6 LSB typical
INL = ±5.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
FUNCTIONAL BLOCK DIAGRAM
CMOS
OR
LVDS
OUTPUT
STAGING
CLOCK
AND TIMING
MANAGEMENT
AGND
DRGND DRVDD
VREF
CLK+
VIN+
AD9461
VIN–
CLK–
DCO
AVDD1 AVDD2
DCS MODE
DFS
OUTPUT MODE
T/H
BUFFER
16
PIPELINE
ADC
2
32
2
OR
D15 TO D0
REF
REFB
SENSE REFT
Figure 1.
APPLICATIONS
MRI receivers
Multicarrier, multimode, cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9461 is a 16-bit, monolithic, sampling, analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
AD9461 operates up to 130 MSPS, providing a superior signal-
to-noise ratio (SNR) for instrumentation, medical imaging, and
radar receivers using baseband (<100 MHz) and IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS compatible
(ANSI-644 compatible) and include the means to reduce the
overall current needed for short trace distances.
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9461 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP_EP) specified over the industrial
temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
True 16-bit linearity.
2.
High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
3.
Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
4.
Packaged in a Pb-free, 100-lead TQFP_EP.
5.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6.
Out-of-range (OR) outputs indicate when the signal is
beyond the selected input range.


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