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XA-G37 Datasheet(PDF) 25 Page - NXP Semiconductors

Part No. XA-G37
Description  XA 16-bit microcontroller family 32K OTP, 512 B RAM, watchdog, 2 UARTs
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

XA-G37 Datasheet(HTML) 25 Page - NXP Semiconductors

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Philips Semiconductors
Product data
XA-G37
XA 16-bit microcontroller family
32K OTP, 512 B RAM, watchdog, 2 UARTs
2002 Mar 25
23
AC ELECTRICAL CHARACTERISTICS (VDD = 2.7 V TO 4.5 V)
Tamb = 0 to +70 °C for commercial, –40 °C to +85 °C for industrial.
SYMBOL
FIGURE
PARAMETER
VARIABLE CLOCK
UNIT
SYMBOL
FIGURE
PARAMETER
MIN
MAX
UNIT
Address Cycle
tCRAR
21
Delay from clock rising edge to ALE rising edge
15
60
ns
tLHLL
16
ALE pulse width (programmable)
(V1 * tC) – 10
ns
tAVLL
16
Address valid to ALE de-asserted (set-up)
(V1 * tC) – 18
ns
tLLAX
16
Address hold after ALE de-asserted
(tC/2) – 12
ns
Code Read Cycle
tPLPH
16
PSEN pulse width
(V2 * tC) – 12
ns
tLLPL
16
ALE de-asserted to PSEN asserted
(tC/2) – 9
ns
tAVIVA
16
Address valid to instruction valid, ALE cycle (access time)
(V3 * tC) – 58
ns
tAVIVB
17
Address valid to instruction valid, non-ALE cycle (access time)
(V4 * tC) – 52
ns
tPLIV
16
PSEN asserted to instruction valid (enable time)
(V2 * tC) – 52
ns
tPXIX
16
Instruction hold after PSEN de-asserted
0
ns
tPXIZ
16
Bus 3-State after PSEN de-asserted (disable time)
tC – 8
ns
tIXUA
16
Hold time of unlatched part of address after instruction latched
0
ns
Data Read Cycle
tRLRH
18
RD pulse width
(V7 * tC) – 12
ns
tLLRL
18
ALE de-asserted to RD asserted
(tC/2) – 9
ns
tAVDVA
18
Address valid to data input valid, ALE cycle (access time)
(V6 * tC) – 58
ns
tAVDVB
19
Address valid to data input valid, non-ALE cycle (access time)
(V5 * tC) – 52
ns
tRLDV
18
RD low to valid data in, enable time
(V7 * tC) – 52
ns
tRHDX
18
Data hold time after RD de-asserted
0
ns
tRHDZ
18
Bus 3-State after RD de-asserted (disable time)
tC – 8
ns
tDXUA
18
Hold time of unlatched part of address after data latched
0
ns
Data Write Cycle
tWLWH
20
WR pulse width
(V8 * tC) – 12
ns
tLLWL
20
ALE falling edge to WR asserted
(V12 * tC) – 10
ns
tQVWX
20
Data valid before WR asserted (data setup time)
(V13 * tC) – 28
ns
tWHQX
20
Data hold time after WR de-asserted (Note 6)
(V11 * tC) – 8
ns
tAVWL
20
Address valid to WR asserted (address setup time) (Note 5)
(V9 * tC) – 28
ns
tUAWH
20
Hold time of unlatched part of address after WR is de-asserted
(V11 * tC) – 10
ns
Wait Input
tWTH
21
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
(V10 * tC) – 40
ns
tWTL
21
WAIT hold after bus strobe (RD, WR, or PSEN) assertion
(V10 * tC) – 5
ns
NOTES:
1. Load capacitance for all outputs = 80 pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL).
Refer to the
XA User Guide for details of the bus timing settings.
V1)
This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register.
V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2)
This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and
ALEW bits in the BTRL register.
For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst
mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of
determining peripheral timing requirements.
For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10,
and 5 if CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5).
Example:
If CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 + 0.5) = 2.


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