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XA-G37 Datasheet(PDF) 21 Page - NXP Semiconductors |
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XA-G37 Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 37 page  Philips Semiconductors Product data XA-G37 XA 16-bit microcontroller family 32K OTP, 512 B RAM, watchdog, 2 UARTs 2002 Mar 25 19 I/O PORT OUTPUT CONFIGURATION Each I/O port pin can be user configured to one of 4 output types. The types are Quasi-bidirectional (essentially the same as standard 80C51 family I/O ports), Open-Drain, Push-Pull, and Off (high impedance). The default configuration after reset is Quasi-bidirectional. However, in the ROMless mode (the EA pin is low at reset), the port pins that comprise the external data bus will default to push-pull outputs. I/O port output configurations are determined by the settings in port configuration SFRs. There are 2 SFRs for each port, called PnCFGA and PnCFGB, where “n” is the port number. One bit in each of the 2 SFRs relates to the output setting for the corresponding port pin, allowing any combination of the 2 output types to be mixed on those port pins. For instance, the output type of port 1 pin 3 is controlled by the setting of bit 3 in the SFRs P1CFGA and P1CFGB. Table 4 shows the configuration register settings for the 4 port output types. The electrical characteristics of each output type may be found in the DC Characteristic table. Table 4. Port Configuration Register Settings PnCFGB PnCFGA Port Output Mode 0 0 Open Drain 0 1 Quasi-bidirectional 1 0 Off (high impedance) 1 1 Push-Pull NOTE: Mode changes may cause glitches to occur during transitions. When modifying both registers, WRITE instructions should be carried out consecutively. EXTERNAL BUS The external program/data bus allows for 8-bit or 16-bit bus width, and address sizes from 12 to 20 bits. The bus width is selected by an input at reset (see Reset Options below), while the address size is set by the program in a configuration register. If all off-chip code is selected (through the use of the EA pin), the initial code fetches will be done with the maximum address size (20 bits). RESET The device is reset whenever a logic “0“ is applied to RST for at least 10 microseconds, placing a low level on the pin re-initializes the on-chip logic. Reset must be asserted when power is initially applied to the XA and held until the oscillator is running. The duration of reset must be extended when power is initially applied or when using reset to exit power down mode. This is due to the need to allow the oscillator time to start up and stabilize. For most power supply ramp up conditions, this time is 10 milliseconds. As it is brought high again, an exception is generated which causes the processor to jump to the address contained in the memory location 0000. The destination of the reset jump must be located in the first 64k of code address on power-up, all vectors are 16-bit values and so point to page zero addresses only. After a reset the RAM contents are indeterminate. VDD R C RST XA SOME TYPICAL VALUES FOR R AND C: R = 100K, C = 1.0 µF R = 1.0M, C = 0.1 µF (ASSUMING THAT THE VDD RISE TIME IS 1ms OR LESS) SU00702 Figure 15. Recommended Reset Circuit RESET OPTIONS The EA pin is sampled on the rising edge of the RST pulse, and determines whether the device is to begin execution from internal or external code memory. EA pulled high configures the XA in single-chip mode. If EA is driven low, the device enters ROMless mode. After Reset is released, the EA/WAIT pin becomes a bus wait signal for external bus transactions. The BUSW/P3.5 pin is weakly pulled high while reset is asserted, allowing simple biasing of the pin with a resistor to ground to select the alternate bus width. If the BUSW pin is not driven at reset, the weak pullup will cause a 1 to be loaded for the bus width, giving a 16-bit external bus. BUSW may be pulled low with a 2.7K or smaller value resistor, giving an 8-bit external bus. The bus width setting from the BUSW pin may be overridden by software once the user program is running. Both EA and BUSW must be held for three oscillator clock times after reset is deasserted to guarantee that their values are latched correctly. POWER REDUCTION MODES The XA-G37 supports Idle and Power Down modes of power reduction. The idle mode leaves some peripherals running to allow them to wake up the processor when an interrupt is generated. The power down mode stops the oscillator in order to minimize power. The processor can be made to exit power down mode via reset or one of the external interrupt inputs. In order to use an external interrupt to re-activate the XA while in power down mode, the external interrupt must be enabled and be configured to level sensitive mode. In power down mode, the power supply voltage may be reduced to the RAM keep-alive voltage (2 V), retaining the RAM, register, and SFR values at the point where the power down mode was entered. |
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