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SSTUB32866 Datasheet(PDF) 27 Page - NXP Semiconductors |
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SSTUB32866 Datasheet(HTML) 27 Page - NXP Semiconductors |
27 / 29 page SSTUB32866_2 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 02 — 9 October 2006 27 of 29 NXP Semiconductors SSTUB32866 1.8 V DDR2-800 configurable registered buffer with parity 15. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes SSTUB32866_2 20061009 Product data sheet - SSTUB32866_1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 1 “Ordering information”: added Type number SSTUB32866EC/S • added Section 4.1 “Ordering options” • Figure 3 “Pin configuration for LFBGA96” modified (added Type number SSTUB32866EC/S) • Table 7 “Recommended operating conditions”, Symbol Tamb: added separate specifications for SSTUB32866EC/G and SSTUB32866EC/S • Table 9 “Timing requirements”, description below table title: changed “See Figure 2.” to “See Section 11.1.” • Table 10 “Switching characteristics”: – changed parameter description of tPDM from “propagation delay” to “peak propagation delay” – changed parameter description of tPDMSS from “simultaneous switching propagation delay” to “simultaneous switching peak propagation delay” • Figure 26 “Partial parity out voltage waveforms; propagation delay times with respect to RESET input”, 4th note: changed “VIL =VDD” to “VIL = GND” SSTUB32866_1 20060518 Product data sheet - - |
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