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PH5525L Datasheet(PDF) 3 Page - NXP Semiconductors |
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PH5525L Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 12 page PH5525L_2 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 02 — 5 December 2006 3 of 12 NXP Semiconductors PH5525L N-channel TrenchMOS logic level FET Fig 1. Normalized total power dissipation as a function of mounting base temperature Fig 2. Normalized continuous drain current as a function of mounting base temperature Tmb =25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 03aa15 0 40 80 120 0 50 100 150 200 Tmb Pder (%) ( °C) 03aa23 0 40 80 120 0 50 100 150 200 (%) Ider Tmb (°C) P der P tot P tot 25 °C () ------------------------ 100 % × = I der I D I D25 °C () -------------------- 100 % × = 003aab437 1 10 10 2 10 3 10 -1 1 10 10 2 VDS (V) ID (A) DC 1 ms 100 µs Limit RDSon = VDS / ID 10 ms 100 ms 10 µs tp = |
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