PCK940LBD datasheet(6/16 Pages) PHILIPS

Part #	PCK940LBD

Description	Low voltage 1 : 18 clock distribution chip

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Manufacturer	PHILIPS [NXP Semiconductors]

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PCK940L_1

Product data sheet

Rev. 01 — 4 April 2006

6 of 16

Philips Semiconductors

PCK940L

Low voltage 1 : 18 clock distribution chip

9.

Dynamic characteristics

[1]

Tested using standard input levels, production tested at 150 MHz.

[2]

Across temperature and voltage ranges, includes output skew.

[3]

For a speciﬁc temperature and voltage, includes output skew.

Table 9.

Dynamic characteristics (3.3 V VCC, 3.3 V output)

Tamb =0 °Cto70 °C; VCC2 = 3.3 V ± 5 %; VCC1 = 3.3 V ± 5%

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

foper(max)

maximum operating frequency

-

250

MHz

tPLH

LOW-to-HIGH propagation

delay

PECL_CLK

≤ 150 MHz

[1] 2.0

2.7

3.8

ns

LVCMOS_CLK

≤ 150 MHz

[1] 1.8

2.5

3.0

ns

PECL_CLK > 150 MHz

2.0

2.9

3.7

ns

LVCMOS_CLK > 150 MHz

1.8

2.4

3.2

ns

tsk(o)

output skew time

output-to-output

PECL_CLK

[1] -

-

200

ps

LVCMOS_CLK

[1] -

-

150

ps

tsk(pr)

process skew time

part-to-part

PECL_CLK < 150 MHz

[1][2] -

-

1.4

ns

LVCMOS_CLK < 150 MHz

[1][2] -

-

1.2

ns

PECL_CLK > 150 MHz

[1][2] -

-

1.7

ns

LVCMOS_CLK > 150 MHz

[1][2] -

-

1.4

ns

PECL_CLK

[1][3] -

-

850

ps

LVCMOS_CLK

[1][3] -

-

750

ps

δo

output duty cycle

LCVMOS_CLK; input

δ =50%

fclk < 134 MHz

45

50

55

%

fclk ≤ 250 MHz

40

50

60

%

PECL_CLK; input

δ =50%

fclk < 134 MHz

35

50

65

%

fclk ≤ 250 MHz

40

50

60

%

tr

rise time

output; from 0.5 V to 2.4 V

0.3

-

1.1

ns

tf

fall time

output; from 2.4 V to 0.5 V

0.3

-

1.1

ns

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