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P89LPC9401 Datasheet(PDF) 46 Page - NXP Semiconductors

Part No. P89LPC9401
Description  8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 32 segment x 4 LCD driver
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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P89LPC9401 Datasheet(HTML) 46 Page - NXP Semiconductors

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P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
46 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment
× 4 LCD driver
10. Dynamic characteristics
Table 12:
Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
Variable clock
fosc = 12 MHz Unit
Min
Max
Min
Max
fosc(RC)
internal RC oscillator frequency
7.189
7.557
7.189
7.557
MHz
fosc(WD)
internal watchdog oscillator
frequency
320
520
320
520
kHz
fosc
oscillator frequency
0
12
-
-
MHz
Tcy(CLK)
clock cycle time
see Figure 18
83
-
-
-
ns
fCLKLP
active frequency on pin CLKLP
0
8
-
-
MHz
Glitch filter
tgr
glitch rejection
P1.5/RST pin
-
50
-
50
ns
any pin except
P1.5/RST
-
15
-
15
ns
tsa
signal acceptance time
P1.5/RST pin
125
-
125
-
ns
any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
see Figure 18
33
Tcy(CLK) − tCLCX
33
-
ns
tCLCX
clock LOW time
see Figure 18
33
Tcy(CLK) − tCHCX
33
-
ns
tCLCH
clock rise time
see Figure 18
-8
-
8
ns
tCHCL
clock fall time
see Figure 18
-8
-
8
ns
Shift register (UART mode 0)
TXLXL
serial port clock cycle time
see Figure 17
16Tcy(CLK)
-
1333
-
ns
tQVXH
output data set-up to clock rising
edge time
see Figure 17
13Tcy(CLK)
-
1083
-
ns
tXHQX
output data hold after clock rising
edge time
see Figure 17
-Tcy(CLK) + 20
-
103
ns
tXHDX
input data hold after clock rising edge
time
see Figure 17
-0
-
0
ns
tXHDV
input data valid to clock rising edge
time
see Figure 17
150
-
150
-
ns
SPI interface
fSPI
SPI operating frequency
slave
0
CCLK
6
0
2.0
MHz
master
-
CCLK
4
-
3.0
MHz
TSPICYC
SPI cycle time
see Figure 19,
20, 21, 22
slave
6
CCLK
-
500
-
ns
master
4
CCLK
-
333
-
ns
tSPILEAD
SPI enable lead time (slave)
see Figure 21,
22
250
-
250
-
ns
tSPILAG
SPI enable lag time (slave)
see Figure 21,
22
250
-
250
-
ns


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