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IP4770CZ16 Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. IP4770CZ16
Description  VGA/video interface with integrated buffers, ESD protection and integrated termination resistors
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com

IP4770CZ16 Datasheet(HTML) 1 Page - NXP Semiconductors

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General description
The IP4770CZ16, IP4771CZ16, IP4772CZ16 is connected between the VGA/DVI
interface and the video graphics controller and includes level shifting for the DDC signals,
buffering for the SYNC lines as well as high-level ESD protection diodes for the RGB
signal lines.
The level shifting functions are required when the DDC controller operates at a lower
supply voltage than the monitor. To use this level shifting function the gates of the two
N-channel MOSFETs have to be connected to the supply rail of the DDC transceivers.
Buffering for the SYNC signals is provided by two non-inverting buffers, which accept TTL
input levels and convert these to CMOS compliant output levels between pins VCC(SYNC)
and GND.
The IP4770CZ16 and IP4771CZ16 contain the formerly external termination resistors,
which are typically required for the HSYNC and VSYNC lines of the video interface:
IP4770CZ16: Rsync = 55 Ω
IP4771CZ16: Rsync =65 Ω
IP4772CZ16: Rsync =10 Ω to allow termination of the SYNC lines
All RGB I/Os are protected by a special diode configuration offering a low line capacitance
of 4 pF (maximum) only to provide protection to downstream components for ESD
voltages as high as
±8 kV contact discharge according to IEC 61000-4-2, level 4 standard.
I Integrated high-level ESD protection, buffering, SYNC signal impedance matching and
level shifting
I Terminal connections with integrated rail-to-rail clamping diodes with downstream ESD
protection of
±8 kV according to IEC 61000-4-2, level 4 standard
I Backflow protection on DDC lines
I Drivers for HSYNC and VSYNC lines
I Bidirectional level shifting N-channel FETs available for DDC clock and DDC data
I Integrated impedance matching resistors on SYNC lines
I Line capacitance < 4 pF per channel
I Lead-free package and RoHS compliant
VGA/video interface with integrated buffers, ESD protection
and integrated termination resistors
Rev. 01 — 25 October 2006
Product data sheet

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