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74AUP2G00 Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. 74AUP2G00
Description  Low-power dual 2-input NAND gate
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74AUP2G00 Datasheet(HTML) 1 Page - NXP Semiconductors

 
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1.
General description
The 74AUP2G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP2G00 provides the dual 2-input NAND function.
2.
Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-D Class 3A exceeds 4000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from
−40 °Cto+85 °C and −40 °C to +125 °C
74AUP2G00
Low-power dual 2-input NAND gate
Rev. 01 — 25 August 2006
Product data sheet


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