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74AUP2G00 Datasheet(PDF) 4 Page - NXP Semiconductors

Part No. 74AUP2G00
Description  Low-power dual 2-input NAND gate
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74AUP2G00 Datasheet(HTML) 4 Page - NXP Semiconductors

 
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74AUP2G00_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 25 August 2006
4 of 16
Philips Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
8.
Limiting values
[1]
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For VSSOP8 packages: above 110
°C the value of P
tot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 45
°C the value of P
tot derates linearly with 2.4 mW/K.
9.
Recommended operating conditions
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
−0.5
+4.6
V
IIK
input clamping current
VI <0V
-
−50
mA
VI
input voltage
[1]
−0.5
+4.6
V
IOK
output clamping current
VO <0V
-
−50
mA
VO
output voltage
Active mode and Power-down mode
[1]
−0.5
+4.6
V
IO
output current
VO =0 VtoVCC
-
±20
mA
ICC
supply current
-
+50
mA
IGND
ground current
-
−50
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
Tamb = −40 °C to +125 °C
[2] -
250
mW
Table 6.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.8
3.6
V
VI
input voltage
0
3.6
V
VO
output voltage
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
Tamb
ambient temperature
−40
+125
°C
∆t/∆V
input transition rise and fall rate
VCC = 0.8 V to 3.6 V
0
200
ns/V


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