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W210H Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. W210H
Description  Spread Spectrum FTG for VIA K7 Chipset
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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W210H Datasheet(HTML) 1 Page - Cypress Semiconductor

 
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Spread Spectrum FTG for VIA K7 Chipset
W210
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
April 11, 2000, rev. *C
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Single-chip system frequency synthesizer for VIA K7
chipset
• One pair of differential CPU outputs for K7 Processor
• One open-drain CPU output for VIA K7 chipset
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 200 MHz
•I2C™ interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
I2C is a trademark of Philips Corporation.
Table 1. Mode Input Table
Mode
Pin 2
0
CPU_STOP#
1REF0
Table 2. Pin Selectable Frequency
Input Address
CPU
(MHz)
PCI0:5
(MHz)
Spread
Spectrum
FS3 FS2 FS1 FS0
1
1
1
1
133.3
33.3
±0.5%
1
1
1
0
75
37.5
±0.5%
1
1
0
1
100.2
33.3
±0.5%
1
1
0
0
66.8
33.4
±0.5%
1
0
1
1
79
39.5
OFF
1
0
1
0
110
36.7
OFF
1
0
0
1
115
38.3
OFF
1
0
0
0
120
30
OFF
0
1
1
1
133.3
33.3
OFF
0
1
1
0
83.3
27.7
OFF
0
1
0
1
100.2
33.3
OFF
0
1
0
0
66.8
33.4
OFF
0
0
1
1
124
31.0
OFF
0
0
1
0
129
32.3
OFF
0
0
0
1
138
34.5
OFF
0
0
0
0
143
35.8
OFF
Block Diagram
Pin Configuration
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
[1]
VDDQ3
REF0/(CPU_STOP#)
PCI0/MODE
XTAL
PLL Ref Freq
PLL 1
X2
X1
REF1/FS0
VDDQ3
Stop
Clock
Control
PCI2
PCI3
PCI4
48MHz/FS2
24_48MHz/FS3
PLL2
÷2,3,4
OSC
PWRDWN#
VDDQ3
PCI5
I2C
SDATA
Logic
SCLK
I/O Pin
Control
SDRAM0:12
SDRAMIN
13
VDDQ3
PCI1/FS1
CPUT0
÷2
CPUT_CS
CPUC0
VDDQ3
REF0/(CPU_STOP#)
GND
X1
X2
VDDQ3
PCI0/MODE
PCI1/FS1*
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDATA
SCLK
REF1/FS0*
GND
CPUT_CS
GND
CPUC0
CPUT0
VDDQ3
PWRDWN#*
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS2*
24_48MHz/FS3^
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I2C
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