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W210H Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. W210H
Description  Spread Spectrum FTG for VIA K7 Chipset
Download  14 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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W210H Datasheet(HTML) 6 Page - Cypress Semiconductor

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W210
6
Writing Data Bytes
Each bit in the data bytes controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 5 gives the bit formats for registers located in Data
Bytes 0–7.
Table 6 details additional frequency selections that are avail-
able through the serial data interface.
Table 5. Data Bytes 0–7 Serial Configuration Map
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1
Data Byte 0
7
--
--
(Reserved)
--
--
0
6
--
--
SEL_2
See Table 6
0
5
--
--
SEL_1
See Table 6
0
4
--
--
SEL_0
See Table 6
0
3
--
--
Hardware/Software Frequency
Select
Hardware
Software
0
2
--
--
SEL_4
See Table 6
1
1
--
--
SEL_3
See Table 6
0
0
--
--
(Reserved)
Normal
Three-stated
0
Data Byte 1
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved) Write to ‘1’
--
--
1
2
--
--
(Reserved) Write to ‘1’
--
--
1
1
--
--
(Reserved) Write to ‘1’
--
--
1
0
--
(Reserved) Write to ‘1’
--
--
1
Data Byte 2
7
--
--
(Reserved)
--
--
0
6
7
PCI0
Clock Output Disable
Low
Active
1
5
--
--
(Reserved)
--
--
0
4
13
PCI5
Clock Output Disable
Low
Active
1
3
12
PCI4
Clock Output Disable
Low
Active
1
2
11
PCI3
Clock Output Disable
Low
Active
1
1
10
PCI2
Clock Output Disable
Low
Active
1
0
8
PCI1
Clock Output Disable
Low
Active
1
Data Byte 3
7
--
--
(Reserved)
--
--
0
6
--
SEL_48MHz
SEL_48MHz as the output fre-
quency for 24_48MHz
24 MHz
48 MHz
0
5
26
48MHz
Clock Output Disable
Low
Active
1
4
25
24_48MHz
Clock Output Disable
Low
Active
1
3
--
--
(Reserved)
--
--
0
2
21, 20,
18, 17
SDRAM8:11
Clock Output Disable
Low
Active
1


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