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IDT72821L20PF Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72821L20PF Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 21 page  5.15 2 COMMERCIAL TEMPERATURE 72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO ™ 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 each FIFO bank to improve memory utilization. If not pro- grammed, the programmable flags default to empty+7 for PAEA and PAEB, and full-7 for PAFA and PAFB. The 72801/72811/72821/72831/72841 architecture lends itself to many flexible configurations such as: • 2-level priority data buffering • Bidirectional operation • Width expansion • Depth expansion This FIFO is fabricated using IDTs high-performance sub- micron CMOS technology. FUNCTIONAL BLOCK DIAGRAM WCLKA WENA2 DA0 - DA8 OFFSET REGISTER INPUT REGISTER RAM ARRAY 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9 WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC OUTPUT REGISTER QA0 - QA8 RCLKA READ CONTROL LOGIC READ POINTER FLAG LOGIC 3034 drw 01A WCLKB WENB2 DB0 - DB8 OFFSET REGISTER INPUT REGISTER RAM ARRAY 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9 WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC OUTPUT REGISTER QB0 - QB8 RCLKB READ CONTROL LOGIC READ POINTER FLAG LOGIC |
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