IS62LV12816BLL

Integrated Silicon Solution, Inc. — 1-800-379-4774

7

Rev. B

03/07/01

1

2

3

4

5

6

7

8

9

10

11

12

-55

-70

-100

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

55

—

70

—

100

—

ns

CE to Write End

50

—

65

—

80

—

ns

Address Setup Time to Write End

50

—

65

—

80

—

ns

Address Hold from Write End

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

ns

LB, UB Valid to End of Write

45

—

60

—

80

—

ns

WE Pulse Width

45

—

60

—

80

—

ns

Data Setup to Write End

25

—

30

—

40

—

ns

Data Hold from Write End

0

—

0

—

0

—

ns

WE LOW to High-Z Output

—

30

—

30

—

40

ns

WE HIGH to Low-Z Output

5

—

5

—

5

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V

and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of

CE LOW and UB or LB, and WE LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced

to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the

CE and WE inputs and at least one

of the

LB and UB inputs being in the LOW state.

2. WRITE = (

CE) [ (LB) = (UB) ] (WE).

AC WAVEFORMS

DATA UNDEFINED

VALID ADDRESS

HIGH-Z

ADDRESS

CE

UB, LB

WE

UB_CSWR1.eps