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IS62LV12816BLL Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc

Part No. IS62LV12816BLL
Description  128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
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Maker  ISSI [Integrated Silicon Solution, Inc]
Homepage  http://www.issi.com
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IS62LV12816BLL Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc

 
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IS62LV12816BLL
ISSI®
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
03/07/01
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-55
-70
-100
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
55
70
100
ns
tSCE
CE to Write End
50
65
80
ns
tAW
Address Setup Time to Write End
50
65
80
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Setup Time
0
0
0
ns
tPWB
LB, UB Valid to End of Write
45
60
80
ns
tPWE
WE Pulse Width
45
60
80
ns
tSD
Data Setup to Write End
25
30
40
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE(3)
WE LOW to High-Z Output
30
30
40
ns
tLZWE(3)
WE HIGH to Low-Z Output
5
5
5
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CE and WE inputs and at least one
of the
LB and UB inputs being in the LOW state.
2. WRITE = (
CE) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t WC
VALID ADDRESS
t SCS
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t PBW
t HD
t SA
t HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
DATAIN VALID
t LZWE
t SD
UB_CSWR1.eps


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