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IDT72201 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72201
Description  CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72201 Datasheet(HTML) 5 Page - Integrated Device Technology

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5.07
5
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V
± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
Commercial and Military
72221L15
72221L20 72221L25
72221L35 72221L50
72231L15
72231L20 72231L25
72231L35 72231L50
72241L15
72241L20 72241L25
72241L35 72241L50
Symbol
Parameter
Min. Max. Min. Max.
Min. Max. Min. Max. Min. Max.
Unit
fS
Clock Cycle Frequency
66.7
50
40
28.6
20
MHz
tA
Data Access Time
2
10
2
12
3
15
3
20
3
25
ns
tCLK
Clock Cycle Time
15
20
25
35
50
ns
tCLKH
Clock HIGH Time
6
8
10
14
20
ns
tCLKL
Clock LOW Time
6
8
10
14
20
ns
tDS
Data Set-up Time
4
5
6
8
10
ns
tDH
Data Hold Time
1
1
1
2
2
ns
tENS
Enable Set-up Time
4
5
6
8
10
ns
tENH
Enable Hold Time
1
1
1
2
2
ns
tRS
Reset Pulse Width(1)
15
20
25
35
50
ns
tRSS
Reset Set-up Time
15
20
25
35
50
ns
tRSR
Reset Recovery Time
15
20
25
35
50
ns
tRSF
Reset to Flag Time and Output Time
15
20
25
35
50
ns
tOLZ
Output Enable to Output in Low-Z(2)
0
0—
0
0—
0
ns
tOE
Output Enable to Output Valid
3
8
3
10
3
13
3
15
3
28
ns
tOHZ
Output Enable to Output in High-Z(2)
3
8
310
3
13
315
3
28
ns
tWFF
Write Clock to Full Flag
10
12
15
20
30
ns
tREF
Read Clock to Empty Flag
10
12
15
20
30
ns
tPAF
Write Clock to Programmable Almost-Full Flag
10
12
15
20
30
ns
tPAE
Read Clock to Programmable Almost-Empty Flag
10
12
15
20
30
ns
tSKEW1
Skew Time Between Read Clock and Write Clock
6
8
10
12
15
ns
for Empty Flag and Full Flag
tSKEW2
Skew Time Between Read Clock and Write Clock
28
35
40
42
45
ns
for Programmable Almost-Empty Flag and
Programmable Almost-Full Flag
NOTES:
2655 tbl 08
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 1
2655 tbl 09
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
30pF*
1.1K
5V
680
D.U.T.
2655 drw 03


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