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IDT72201 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT72201
Description  CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72201 Datasheet(HTML) 2 Page - Integrated Device Technology

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5.07
2
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
D0-D8
Data Inputs
I
Data inputs for a 9-bit bus.
RS
Reset
I
When
RS is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after
power-up.
WCLK
Write Clock
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
WEN1
Write Enable 1
I
If the FIFO is configured to have programmable flags,
WEN1 is the only write enable pin.
When
WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables,
WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the
FF is LOW.
WEN2/
LD Write Enable 2/
I
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
Load
LD is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables,
WEN1 must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the
FF is LOW. If the FIFO is config-
ured to have programmable flags, WEN2/
LD is held LOW to write or read the programmable flag
offsets.
Q0-Q8
Data Outputs
O
Data outputs for a 9-bit bus.
RCLK
Read Clock
I
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN1 and REN2 are
asserted.
REN1
Read Enable 1
I
When
REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the
EF is LOW.
REN2
Read Enable 2
I
When
REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the
EF is LOW.
OE
Output Enable
I
When
OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
EF
Empty Flag
O
When
EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
O
When
PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
Almost-Empty
The default offset at reset is Empty+7.
PAE is synchronized to RCLK.
Flag
PAF
Programmable
O
When
PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
Almost-Full Flag
default offset at reset is Full-7.
PAF is synchronized to WCLK.
FF
Full Flag
O
When
FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full.
FF is synchronized to WCLK.
VCC
Power
One +5 volt power supply pin.
GND
Ground
One 0 volt ground pin.
2655 tbl 01
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
5
6
7
8
9
10
11
12
13
CC
8
7
6
5
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
D
27
26
25
24
23
22
21
29
28
432
1
32 31 30
14 15 16 17 18 19 20
J32-1
L32-1
INDEX
2655 drw 02
TQFP
TOP VIEW
LCC/PLCC
TOP VIEW
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
5
6
7
8
16
CC
8
7
6
5
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
D
27 26 25
24
23
22
21
29 28
32 31 30
9 1011 12131415
2655 drw 02a
1
2
3
4
20
19
18
17
PR32-1
INDEX


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