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GM71C17403C Datasheet(PDF) 4 Page - Hynix Semiconductor

Part No. GM71C17403C
Description  4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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GM71C17403C Datasheet(HTML) 4 Page - Hynix Semiconductor

 
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GM71C(S)17403C/CL
Rev 0.1 / Apr’01
Capacitance (VCC = 5V+/-10%, TA = 25C)
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 2, 18, 19)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
Note
CI1
CI2
CI/O
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
1
1
1, 2
Unit
pF
pF
pF
Max
5
7
7
Min
-
-
-
Test Conditions
Input rise and fall times: 2 ns
Input timing reference levels: 0.8V, 2.4V
Output timing reference levels: 0.8V, 2.0V
Output load : 1 TTL gate + CL (100pF)
(Including scope and jig)
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
Symbol
Parameter
Note
Max
Unit
Min
Max
Min
Max
Min
tRC
84
-
104
-
124
-
tRP
30
-
40
-
50
-
tRAS
50 10,000
60 10,000
70 10,000
tCAS
7 10,000
10,000
10,000
10
13
tASR
0
-
-
-
0
0
tRAH
7
-
-
-
10
10
tASC
0
-
-
-
0
0
tCAH
7
-
-
-
10
13
tRCD
11
37
45
52
14
14
3
tRAD
9
25
30
35
12
12
4
tRSH
10
-
-
-
13
13
tCSH
35
-
-
-
40
45
tCRP
5
-
-
-
5
5
tT
2
50
50
50
2
2
7
tDZO
0
-
-
-
0
0
tDZC
0
-
-
-
0
0
GM71C(S)17403
C/CL-5
13
-
-
-
15
18
5
6
6
tCP
7
-
10
-
13
-
Random Read or Write Cycle Time
RAS Precharge Time
RAS Pulse Width
CAS Pulse Width
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
Transition Time (Rise and Fall)
OE Delay Time from DIN
CAS Delay Time from DIN
OE to DIN Delay Time
CAS Precharge Time
tODD
GM71C(S)17403
C/CL-6
GM71C(S)17403
C/CL-7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
21
22
24


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