Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

CY8C9520 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. CY8C9520
Description  20-, 40-, and 60-Bit I/O Expander with EEPROM
Download  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C9520 Datasheet(HTML) 1 Page - Cypress Semiconductor

  CY8C9520 Datasheet HTML 1Page - Cypress Semiconductor CY8C9520 Datasheet HTML 2Page - Cypress Semiconductor CY8C9520 Datasheet HTML 3Page - Cypress Semiconductor CY8C9520 Datasheet HTML 4Page - Cypress Semiconductor CY8C9520 Datasheet HTML 5Page - Cypress Semiconductor CY8C9520 Datasheet HTML 6Page - Cypress Semiconductor CY8C9520 Datasheet HTML 7Page - Cypress Semiconductor CY8C9520 Datasheet HTML 8Page - Cypress Semiconductor CY8C9520 Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 25 page
background image
August 17, 2005
© Cypress Semiconductor Corp. 2005 — Document No. 38-12036 Rev. *A
1
Cypress Semiconductor
Preliminary Data Sheet
CY8C9520,
CY8C9540, and CY8C9560
20-, 40-, and 60-Bit I/O Expander with EEPROM
Features
I2C™ interface logic electrically compatible with SMBus.
Up to 20 (CY8C9520), 40 (CY8C9540) or 60 (CY8C9560)
I/O data pins independently configurable as inputs, outputs,
bi-directional input/outputs or PWM outputs.
4/8/16 PWM sources with 8-bit resolution.
Extendable Soft Addressing™ algorithm allowing flexible
I2C-address configuration.
Internal 3-/11-/27-Kbyte EEPROM.
Storage of user defaults and I/O port settings in the internal
EEPROM.
Optional EEPROM Write Disable (WD) input.
Interrupt output indicates input pin level changes and pulse
width modulator (PWM) state changes.
Internal power-on reset (POR).
Figure 1-1. Top Level Block Diagram
Overview
The CY8C95xx is a multi-port I/O expander with on-board user-
available EEPROM and several PWM outputs. All devices in
this family operate identically but differ in I/O pins, number of
PWMs, and internal EEPROM size.
The CY8C95xx operates as two I2C slave devices. The first
device is a multi-port I/O expander (single I2C address to
access all ports via registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to dis-
able the EEPROM. The EEPROM utilizes 2-byte addressing to
support the 28-Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I2C address
or by specific register addressing.
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM
ouputs. The individual data pins can be configured as open
drain/collector, strong drive (10 mA source, 25 mA sink), resis-
tively pulled-up/-down, or high-impedance. The factory default
configuration is pulled-up internally.
The system master writes to the I/O configuration registers via
the I2C bus. Configuration and output register settings can be
stored as user defaults in a dedicated section of the EEPROM.
If user defaults have been stored in EEPROM, they are
restored to the ports at power-up. While this device can share
the bus with SMBus devices, it can only communicate with
I2C-masters.
There is one dedicated pin that is configured as an interrupt out-
put (INT) and can be connected to the interrupt logic of the sys-
tem master. This signal can inform the system master that there
is incoming data on its ports or that the PWM output state was
changed.
The EEPROM is byte-readable and supports byte-by-byte writ-
ing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The con-
figuration registers can also disable EEPROM operations.
The CY8C95xx has one fixed address pin (A0) and up to six
additional pins (A1-A6) which allow up to 128 devices to share a
common two-wire I2C data bus. The Extendable Soft Address-
ing algorithm provides the option to choose the number of pins
needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
EEPROM
User
Settings
Area
User
Available
Area
Control
Unit
GPort 0
GPort 1
GPort 2
GPort 3
GPort 7
PWM 0
PWM 15
Pow er-on-Reset
1.5 MHz
93.75 kHz
Divider (1-255)
Clocks
32 kHz
24 MHz
WD
SCL
SDA
V
dd
V
ss
8 Bit I/O
5 Bit I/O
3 Bit I/O
or A4-A6
4 Bit I/O
or A1-A3, W
8 Bit I/O
8 Bit I/O
INT
A0


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn