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CY8C9520 Datasheet(PDF) 9 Page - Cypress Semiconductor

Part No. CY8C9520
Description  20-, 40-, and 60-Bit I/O Expander with EEPROM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C9520 Datasheet(HTML) 9 Page - Cypress Semiconductor

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August 17, 2005
Document No. 38-12036 Rev. *A
9
CY8C95xx Preliminary Data Sheet
2. Pinouts and Pin Descriptions
2.2
PIN Descriptions
2.2.1
Extendable Soft Addressing™
The A0 line is always used to define the corresponding bit of the
I2C address. This pin should be pulled up or down. If A0 is a
strong pull-up or a strong pull-down (wired through 330 or less
resistor to Vdd or Vss), then that is the only address line being
specified and the A1-A6 lines are used as GPIO. If A0 is a weak
pull-up or a weak pull-down (connected to Vdd or Vss through
75K- 200K-ohm resistor), then A0 is not the only externally
defined address bit. There is a pin assigned to be A1 if it is
needed. This pin can be pulled-up or pulled-down strong or
weak with a resistor. As with A0, the type of pull determines
whether the address bit is the last externally defined address
bit. Differently from A0, A1 is not dedicated as an address pin. It
is only used if A0 is not the only address bit externally defined.
There are also predefined pins for A2, A3, A4, A5 and A6 that
will only be used for addressing if needed. The last address bit
in the chain is pulled strong. That way, only the number of pins
needed to assign the address desired for the part are allocated
as address pins, any pins not used for address bits are avail-
able to be used as GPIO pins. The Table , “Device Addressing,”
on page 3 defines the resulting device I2C address.
2.2.2
Interrupt Pin (INT)
The interrupt output (if enabled) is activated if one of the follow-
ing events occurs:
One of the GPIO port pins changes state and the corresponding bit
in the Interrupt Mask register is set low.
When a PWM driven by the slowest clock source (367.6 Hz) and
assigned to a pin changes state and the pin’s corresponding bit in
the Interrupt Mask register is set low.
The interrupt line is deactivated when the master device per-
forms a read from the corresponding Interrupt Status register.
2.2.3
Write Disable Pin (WD)
If this feature is enabled, ‘0’ allows writes to the EEPROM and
‘1’ blocks any memory writes. This pin is checked immediately
before performing any write to memory. If the EEE bit in the
Enable register is not set (EEPROM disabled) or bit EERO is
set (EEPROM is read-only) then WD line level is ignored.
Note that ‘1’ on this line blocks all commands which perform
operations with EEPROM (see Table 3-9, “Available Com-
mands,” on page 14).
This line may be enabled/disabled by bit 1 of the Enable regis-
ter (2Dh): ‘1’ enables WD function, ‘0’ disables.
2.2.4
External Reset Pin (XRES)
A full device reset is caused by pulling the XRES pin high. The
XRES pin has an always-on pull-down resistor, so it does not
require an external pull down for operation. It can be tied
directly to ground or left open. Behavior after XRES is similar to
POR.
2.2.5
Working with PWMs
There are four independent PWMs in the CY8C9520, eight in
the CY8C9540 and sixteen in the CY8C9560. Each I/O pin can
be configured as a PWM output by writing ‘1’ to the correspond-
ing bit of the Select PWM register (see Table 3-2, “Output and
Select PWM Registers Logic,” on page 127).
The next step of PWM configuration is clock source selection
using the Config PWM registers. There are six available clock
sources: 32 kHz (default), 24 MHz, 1.5 MHz, 93.75 kHz, 367.6
Hz or previous PWM output. (see Figure 2-1).
Figure 2-1. Clock Sources
By default, 32 kHz is selected as the PWM clock.
PWM Period registers are used to set the output period:
Equation 1
Allowed values are between 1 and FFh.
The PWM Pulse Width register sets the duration of the PWM
output pulse. Allowed values are between zero and the (Period-
1) value. The duty cycle ratio can be computed using the follow-
ing equation:
Equation 2
Divider (1-255)
93.75 kHz
367.6 Hz -
93.75 kHz
1.5 mHz
24 mHz
32 kHz
t
OUT
Period
t
CLK
×
=
DutyCycle
PulseWidth
Period
------------------------------
=


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